The spade-lang.org website has looked largely the same the past 3 years, while the language itself has evolved massively. It was clearly high time for a re-design

I'm extremely excited for this. As far as I know, this is the biggest project anyone else has written in Spade, and certainly the biggest that has been taped out :)

What open source ASIC tools am I excited by in 2025? OpenEMS, 3D viewers, Surfer, OpenROAD, and lots more! Check this article for all the links: zerotoasiccourse.com/post/excited... #opensource #ASIC #tools

Today we release Spade v0.15 🎉 This release includes - Improvements to lambda units - Pipeline methods - Much improved dependency handling - Several additions to the standard library - Better Verilog interop A lot more Release blog blog.spade-lang.org/v0-15-0/ Change log gitlab.com/spade-lang/s...

A few weekends ago I wrote a logic analyzer in Spade 🐠, and it took less than 4 hours I figured I'd write a blog post to show how that was possible and how the code works: blog.spade-lang.org/quickscope/

I finally got around to doing another Surfer release, so now we're on v0.4.0 🎉 My personal highlights are the new web assembly based translator system, and the improvements to our waveform control protocol, and you can read the full change log at gitlab.com/surfer-proje...

please enjoy: my Wasm-hosted, Wasm-targeting build of Clang/Clang++/LLD: a self-contained, 25 MiB (gzipped) pure function www.npmjs.com/package/@yow...

I'm bad at self-promo but I am currently on the job market looking for industry gigs. If your team needs a compiler engineer, language developer, rust programmer, or language tools person, drop me a line! All my details are on my personal site.

I sometimes stream Spade dev over at twitch.tv/thezoq2. Today i'm going to work on clock domain inference, which I think I finally have a good plan for again

I got inspired at orconf, so now play.spade-lang.org supports a full in-browser flow for submitting to tinytapeout.com/ Still experimental, so if you try it and run into any issues, let me know :)

We are hiring! Both technical and admin, please take a look at our jobs page! www.yosyshq.com/jobs #jobs #hire

This Friday I successfully defended my PhD 🎉 If you want to watch a recording of the defense there is a recording here vimeo.com/1114208379/89dcd4f302

This is one of the better succinct summaries of Rust's value prop, and I really like the phrasing of "Rust exposes impedence mismatches": it feels annoying to some people, but often you WANT to be able to "see" these awkward steps, because it matters. news.ycombinator.com/item?id=4497...

Want to help build a crowdsourced microcontroller? You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real! Take part for free! tinytapeout.com/competitions...

Our CAV paper on Surfer is now available online doi.org/10.1007/978-... In it, we talk about the user facing stuff like extensible translators, how Surfer is designed to be extensible and embeddable, and we describe our waveform parsing library - Wellen.

Post a meme made by you

After 2 skipped releases due to me finishing my thesis, it is time for Spade 0.14.0 🎉 This brings long awaited lambda functions into the language, new standard library functions that use them, and a much improved LSP Release blog post: blog.spade-lang.org/v0-14-0/

Something you may hopefully did not notice about my thesis is that the whole thing was written in @typst.app I wrote a few words about why, what I liked, and what I didn't like about it for such a big document fransskarman.com/phd_thesis_i... TL;DR 8/10, would recommend

There it is 👀

My thesis is now published online! 🎉 urn.kb.se/resolve?urn=...

My thesis is now published online! 🎉 urn.kb.se/resolve?urn=...

I’d like to formally propose that academic journals (specifically those in bioinformatics and Cs, but more generally) begin accepting manuscripts prepared with @typst.app. I mean not only for initial submission (where PDF is often sufficient), but for submission of accepted manuscripts as well!

A year ago on a video I said science direct was trash but look at it nowwww... AI garbage. Why read an article??? Why not just let this algorithm spit garbage at you instead? Research!

This seems like really solid advice to me!

Me and a friend (Well mostly my friend, she did most of the design work) built a fully analog flappy bird last weekend No digital logic, just ~30 op amps and 70-80 resistors, a bunch of capacitors and a few analog switches. All assembled during a 48 hour game jam

Do you love Rust, Typst, and Open Source? You may have found your dream job. Typst is looking for a Rust software engineer to work on the Typst compiler. Join us in Berlin or remotely anywhere from Germany or France. Learn more and apply: typst.app/jobs/

On Sunday we're hosting LATTE ☕, our workshop on Languages and Tools for Accelerator design! We have 15 super cool papers and plenty of time for discussion! You can attend virtually via zoom or in person with #asplos in Rotterdam capra.cs.cornell.edu/latte25/

Oh hell yes, working ARP response + ICMP ping request/replies on my #fpga!

My ARP impl in Spade now works, my computer can ask who has the IP address of the #FPGA, and it replies correctly :) Still incredibly pleased with this stream based network packet API. It makes packet transformation super easy, and nicely decouples "fmax buffers" and fifos from behaviour

☕️ Our little workshop about accelerator design languages & tools is next weekend, on March 30! We have 15 cool talks lined up, and the 2-page papers are out now: capra.cs.cornell.edu/latte25/ Make your travel plans to Rotterdam! Or pre-register for the Zoom option: cornell.zoom.us/meeting/regi...

And there it is, the slowest #riscv core? Running on the time multiplexed NAND gate (bsky.app/profile/thez...) The display is showing the PC value. It is running a program to add 1 to a register, and it with 1, and skip an instruction if the result is 0

My hot chip design take is we should rewrite all chip design, EDA, VLSI, and physical design tools in Rust The tooling around packaging and building alone makes it orders of magnitude better than C++ Plus, Rust's focus on fearless concurrency and memory safety is a huge plus for EDA software

I may be straight and cis but I’ll always be proud of trying to make a place where people can feel like they can be themselves without worrying about how that will be perceived. Rust’s culture is far from perfect but I think we set the right tone at the start.

Today we're releasing Spade 0.13.0, one of the biggest releases so far 🎉 The main addition is "gen if" which enables compile time recursion and lays the groundwork for more powerful generic programming Namespaces and external Verilog interaction has also been improved blog.spade-lang.org/v0-13-0/

The SystemVerilog standard is wild. 1300 pages that manage to say absolutely nothing about how the language works, apart from gems like this

👋 Hi, I’m Max! Principal Engineer @ Intel & lead of ROHD, an open-source project making hardware design more fun & accessible. Passionate about hardware, software, open source, and Dart. Also snowboarding, gaming, & new tech! #introduction #opensource #hardware #FPGA #SoC #Dart #HDL #ROHD

It works!!!

You still have almost 2 weeks to submit papers to LATTE ☕ - our workshop on languages, tools, and techniques for accelerator design capra.cs.cornell.edu/latte25/ Papers are 2 pages and should spark discussion, so we encourage work in progress ideas and projects! Deadline: Jan 31 Workshop: March 30

Learn PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @Raspberrypi. This intro covers #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS www.youtube.com/watch?v=wWdv...

Help, i've become addicted to streaming Spade development www.twitch.tv/thezoq2 Let's see if I can use the new changes to the language to build a cache #fpga

☕️ We’re running LATTE again: our ASPLOS workshop about languages/compilers/tools/whatever for hardware design. Submissions are just little 2-pagers, due on January 31. Plenty of time to throw something together! capra.cs.cornell.edu/latte25/

It is time for the most boring Spade release yet 🎉 Boring is good though, it includes 13 bug fixes, along with a system for preventing previously common code gen bugs in the future. Other changes include Gowin #fpga support, and methods on non-named types blog.spade-lang.org/v0-12-0/

If you're working in the general area of languages and/or accelerators, you should absolutely submit a paper! I'm biased of course, but LATTE always has a ton of great people and interesting discussion so I hope to see everyone there :) Submissions close on Jan 31 The workshop is on March 30

finally finished the fiber laser vid! you can check out the full version on yt: youtu.be/wAiGCyZZq6w

On Sunday it will be exactly 2 years since I made the first commit to Surfer 🍰 🎉. To celebrate, we're releasing Surfer version 0.3.0 that contains over half a year of new features and fixes! Blog post: blog.surfer-project.org/v0-3-0/ Changelog: gitlab.com/surfer-proje...

To help others progress, I’m going to award several Christmas test gear grants. If you’re interested, apply here: www.zerotoasiccourse.com/post/test-eq...

Throughout my career I’ve collected a nice set of Strong Opinions about relatively unimportant things. Here’s one: Don’t end your talk with a slide that just says “Thanks!” or “Questions?” The slide that remains up during audience questions should be a summary of your main points

Hello World! ✨ Clash is an open source functional hardware description language built on #Haskell, so if #FPGA, #ASIC and #Haskell are right up your alley, check out our website (link in bio) and give us a follow, we'll be posting more in the future :)

Have you ever wondered how Yosys prepares your design for an #FPGA? In the next Yosys Users Group, our own Krystine will walk us through the synth_ice40 command, how it works and what's going on behind the scenes! Monday 16th December at 9:00 PT / 18:00 CET / 22:30 IST