"How do FPGAs execute blocking assignments in one clock cycle?" Is the perfect question to frame common learning curve hurdles that folks need to get over when learning HDL. www.reddit.com/r/FPGA/comme... #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

How to send a struct from one dev board to another? A PipelineC Story #hdl #hls #RTL #fpga #ethernet #i2s #hardware www.reddit.com/r/FPGA/comme...

implemented a xilinx virtual cable applet. this way you can connect vivado to glasgow and program any supported FPGA glasgow-embedded.org/latest/apple...

#FPGA Congrats to Prof. Jason Cong, for Chuck Thacker Breakthrough in Computing Award, recognized for "fundamental contributions to the design and automation of field-programmable systems and customizable computing". insidehpc.com/2025/04/jaso... C-to-gates was a dream until Cong made it real.

Check out @[email protected] 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL ! #dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware www.linkedin.com/pulse/16-aps...

What can you do with reading arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes), write a little #python script that launches #GTKWave, and you have a tiny homemade cross platform logic analyzer thing! github.com/JulianKemmer...

#hardware debugging and wanted to see some #ethernet MAC address registers down in my pico-ice #ice40 #fpga design. Don't want manufacturer specific ILAs. Don't want to route signals to top, external #debug equipment I don't have. Just assign to #UART debug probe wire: github.com/JulianKemmer...

Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying so I have revived the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and will demo that on the pico ice

Yay those cheap #hardware #ethernet phy #pmod -LIKE things work with the pico-ice #ice40 #FPGA . Thanks for your help with RMII interface @[email protected]! #embedded #HDL #RTL #Verilog #VHDL #HLS github.com/JulianKemmer...

👋 Hi, I’m Max! Principal Engineer @ Intel & lead of ROHD, an open-source project making hardware design more fun & accessible. Passionate about hardware, software, open source, and Dart. Also snowboarding, gaming, & new tech! #introduction #opensource #hardware #FPGA #SoC #Dart #HDL #ROHD

I taped out a variety of adders on open source silicon and Kogge-Stone adders were the fastest for all widths above 8 bits. Yosys now has plugins to choose which topology you want! Read more here: www.zerotoasiccourse.com/post/instrum...

Come learn some PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @raspberrypi.com. This intro talk will cover #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS

In the mood for the littlest bit of #FPGA #GameDev? 🤓 Check out this pico-ice based pong demo. Just need #VGA #pmod and #UART connected to host PC. #HDL #hardware #RTL #Verilog #VHDL #HLS #lattice #ice40 github.com/JulianKemmer...

Gifted a new #FPGA dev board this season? 🤓 PipelineC aims to make #hardware description easier for #embedded folks. Check out the new getting start page. Happy to help you get going! #hdl #verilog #vhdl #hls github.com/JulianKemmer...

Part of why FPGAs are amazing is getting to be part of this hard 💪 hardware world while getting a relatively faster recompile and test cycle like software. I♥️#FPGA

To help others progress, I’m going to award several Christmas test gear grants. If you’re interested, apply here: www.zerotoasiccourse.com/post/test-eq...

Hello World! ✨ Clash is an open source functional hardware description language built on #Haskell, so if #FPGA, #ASIC and #Haskell are right up your alley, check out our website (link in bio) and give us a follow, we'll be posting more in the future :)

If you like thinking like: computers are the best thing humans have ever invented, ~= ASICs are practically pinnacle of science/innovation etc then an FPGA on your desk at home is this magical window into literally the coolest thing humans have ever done ~ computer architecture / digital design 🤓

Have been super pleased with the ice40 #FPGA and #raspberrypi board that pico-ice.tinyvision.ai sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice 🤓 #HDL #Verilog #VHDL #hardware #embedded

I have a blog series on FPGA graphics: projectf.io/posts/fpga-g... with open-source designs for many dev boards including with Yosys. No ads or cookies.

😅😅😅😅😅😅😅😅😅 great post!

since more people are joining bluesky, time for a re-intro! i work on programming languages and compilers for hardware design and will be starting at MIT next year where i will lead the Foundations of Languages and Machines Lab (flame.csail.mit.edu). if the ideas excites you, reach out to me!

Hve you tried an alternative to #verilog or #vhdl? Not only does @thezoq2.bsky.social work on their own very cool Spade #rust inspired #HDL (and Surfer waveform viewer!) but they kindly have this awesome list to browse through too! 🤩 🤓 #fpga #rtl #asic #eda gitlab.com/TheZoq2/list...

the RTL debugger i'm working on can now show diagnostics in-line in the source code :D

PipelineC is a really neat approach to HDL design! A lot of PipelineC is valid C and can be "simulated" by just running it, but where it makes sense it also has hardware specific semantics that make it very different from high level synthesis Oh, and the automatic pipelining is also very cool!

Enjoying dreaming of a world better than #Verilog or #VHDL? Come chat over on the #PipelineC Discord 🤓 Trying to make #HDL #RTL easier to write. Folks with #embedded experience, ever written #C for a #microcontroller with #hardware in mind, should feel right at home in #FPGA discord.gg/Aupm3DDrK2

Last week spoke at the first annual Soft #RISCV Systems Workshop 🔥 about a #hardware #SoC in #FPGA made using #PipelineC for doing #DSP computing #FFT with custom hardware. Can see slides here (no recording): docs.google.com/presentation... #RISC-V #eda #asic #hls #rtl #hdl #verilog #vhdl

'Shared Resource Buses': Multiple 'threads' of C function derived state machines share resources (memory, compute, etc) via AXI-like buses and arbitration. Reach out if you want to make something together! github.com/JulianKemmer... #rtl #hdl #hls #vhdl #verilog #asic #hardware #multithreaded #hpc

Use #PipelineC to listen to FM #radio with an #FPGA #SDR! Huge thanks to @[email protected] and @Darkknight512 for making first version a great learning experience. And @deepwavedigital for the fantastic hardware platform and workplace <3 #hardware #hdl #hls #asic github.com/JulianKemmer...

Several talks in one. #eda #asic #fpga #hdl Can't share enough. Thanks for the great talk Rice! youtu.be/R2ak8KVo0F0

Prototype FPGA placer I wrote to learn Rust. Uses a really basic simulated annealing approach. Hope to integrate into an ongoing research project down the road. #fpga #eda #chipdesign stefanabikaram.com/writing/fpga...

You Bluesky folks seen this awesome work? First raytraced game thats not software? 1080p realtime, interactive, fixed+float point, 3D vector math, no CPU, no instructions, autopipelined in #FPGA! #raytracing #graphics #hardware #gamedev #hdl #verilog #vhdl #eda youtu.be/hn3sr3VMJQU