Eurythmics music video graphics from 1985 🔥 youtube.com/watch?v=gf_O...

It's Friday afternoon, the weather is lousy, you're still working… must be time for #Ceefax music. 👌 www.youtube.com/watch?v=Oc1m...

Yesterday, I discovered a 959416035780 byte log file on a client server. Enough to write a post about every year the Universe has existed.

If you're writing assembler, I heartily recommend Compiler Explorer. I wrote about this from a RISC-V perspective a while back. #asm #riscv projectf.io/posts/riscv-...

I finally got around to doing another Surfer release, so now we're on v0.4.0 🎉 My personal highlights are the new web assembly based translator system, and the improvements to our waveform control protocol, and you can read the full change log at gitlab.com/surfer-proje...

🏝️ Isle #FPGA Computer now has a Verilog 2D graphics engine. Blog: projectf.io/isle/2d-draw... Code: github.com/projf/isle

"Business at the Scottish Parliament has been suspended because of technical issues with the parliament's online voting system. A senior Scottish Parliament source told BBC News they believe the problems are related to the Microsoft outage." Source: www.bbc.co.uk/news/article...

Stormy weather brings mixed emotions. 🌊⛈️ “Cyclonic becoming westerly or northwesterly, 6 to gale 8, occasionally severe gale 9 at first in east. Moderate or rough, increasing very rough for a time. Showers, then rain later, perhaps thundery. Good, becoming moderate or poor later.“

I realise I've been a little quiet on the 🏝️ Isle #FPGA computer over the last month, but I've been beavering🦫 away on the 2D drawing engine, including 8 new Verilog modules, docs, tests, and a blog post. You can see a screenshot from the draft blog post below. More news soon…

I love to hear about interesting accounts to follow for #FPGA, #riscv, #oshw, and #permacomputing. 💛

I meant to type the word "hardware"; I typed the word "garden" instead. It would be nice to think this reflected a deeper truth, but it's probably my mind telling me to stop looking at Verilog. 🤔

I've been upgrading servers to Debian 13. "The overall disk usage for trixie is 403,854,660 kB (403 GB), and is made up of 1,463,291,186 lines of code." 1.5 billion lines of code. 🤔

Happy #FPGAFriday. The hardware for the next installment of 🏝️ Isle #FPGA Computer is ready; now I'm working on docs, a new blog post, and an update for my sponsors. I'm aiming for a public update next Friday. [1/2]

I don't use Google search, but thought I would test its AI Overview. I'm a convert! 😉🍪

Serendipity brought us to Time Circus in Turnhout. “Feel free to look into and open everything”

Over the weekend I released the next part of Isle #FPGA Computer covering bitmap graphics. projectf.io/isle/bitmap-... I've added more docs and tests, but I'm still finding the right approach to the Isle blog and working on diagrams.

Congratulations @clairexen.bsky.social: #HotChips / IEEE TCMM 2025 Open Source Hardware Contribution Award

Party Fears Two

Some friendly advice from Microsoft on the use of AI in Excel. “Avoid using COPILOT for: Numerical calculations…” support.microsoft.com/en-us/office...

No FPGA for me today 😢, so I'd appreciate hearing about your hardware projects. #FPGAFriday

Isle 🏝️ is my new #FPGA project. Isle is a simple, modern computer — an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer. projectf.io/isle/fpga-co...

I'm getting to grips with more cocotb tests for Isle #FPGA computer. This new test verifies pixel output end-to-end: address_calc > vram > clut > display. We're not letting any latency issues sneak in. Will be part of chapter 2: bitmaps.

For some time @securelyfitz.bsky.social and I have been working on a new hardware security tool. A tiny m.2 WiFi module sized FPGA board allowing the access to the PCIe interface. You can sign up for updates for when the campaign launches, some time next year. #EpicErebus #fpga

I’m sad that smaller laptops seem to be a thing of the past. Where are the 10”-12” laptops for writers, travellers, and techies on the move? I want a proper keyboard for writing on, developing on, and SSH. 🤔

“RISC architecture is going to change everything.” Have you seen my seven-part Guide to #riscv assembler? No ads or crappy popups. projectf.io/posts/riscv-...

Icepi Zero looks like an interesting open-source ECP5 #FPGA dev board. It’s got a decent spec in a small form factor. The only obvious omission is audio out. The big question is, how much will it cost? www.crowdsupply.com/icy-electron...

“No 9000 computer has ever made a mistake or distorted information.”

Isle 🏝️ is my new #FPGA project. Isle is a simple, modern computer — an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer. projectf.io/isle/fpga-co...

In honor of the upcoming ICLAD conference, here’s a gem from one of the first LLM-for-hardware-design panels that was at ICCAD. How far we have come.

I love to hear about interesting accounts to follow for #FPGA, #riscv, #oshw, and #permacomputing. 💛

New RP2350 stepping just dropped, E9 fixed. www.raspberrypi.com/news/rp2350-...

Be not afeard; the isle is full of noises, Sounds, and sweet airs, that give delight and hurt not. 🏝️

Want to help build a crowdsourced microcontroller? You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real! Take part for free! tinytapeout.com/competitions...

As I did not post for a long time I will start from an end. We got #ULX5M-GS up and running!!! #CM5 pin compatible #FPGA #SoM with #EU Cologne #GateMate A1 and fully open source toolchain. Still lots of work left, but I am really happy to see DVI out!

My MacBook Air battery life has sucked recently, and it occurred to me to check if I'd left a Verilator simulation running. Instead, I found dot(1) with over 1500 minutes of CPU time! MOAR DoTs! 😉

"We think this machine will be a great success: if that happens the #Amiga will probably have a great effect on other personal computer companies and the industry in general." — Byte August 1985

# I pictured a rainbow # You held it in your hands

You really know dinosaurs didn’t go extinct when they look you in the eye through the kitchen window. 🦕

We've tested 2, 4, and 16 colours, so why not 256? All colour depths supported by the 32-bit bram design with bit (sic) write. 32 x ECP5 brams is 64 KiB, which fits nicely in 25F+. Shown here with ULX3S #FPGA dev board.

I think i got something in the 16 bit RISC ISA department. I only need to finish designing the MMU control register signals. It is also my first ISA supporting (half precision) floats so i can finally start doing 3D stuff. Currently on a first Logisim implementation before going to Verilog

Two word vs byte addressing bugs were cancelling each other out. The life of the hardware developer! 😬 #FPGA

Fitting in some #FPGA time on a Sunday during poor weather. I'm making my canvas (bitmap) addressing modules for display and drawing consistent and 32-bit ready. Strangely satisfying to do this routine stuff sometimes.

Time to test out packed monochrome images on my #FPGA graphics hardware. This is a 672x384 monochrome version of the crocus photo I've been using. Yes, it is Floyd–Steinberg dithering.

Pan pipes have never sounded so cool. #amiga www.youtube.com/watch?v=t5G3...

I’ve completed my year-long journey to becoming a published author in electrical engineering. Mastering FPGA Chip Design: For Speed, Area, Power, and Reliability is now part of the Elektor Academy Pro series and available in both print and eBook formats: www.elektor.com/products/mas...

Testing the Lakritz #FPGA dev board courtesy of Machdyne. DVI video output with my test crocus image. The small, yet solid 3D-printed case makes it feel like a proper little computer.

I've started moving my blog to a simple HTML design in preparation for a new FPGA series. I've only changed the homepage so far, but I'm enjoying working directly in HTML. projectf.io

I've updated my Python tool for converting images (PNG, JPEG etc.) to Verilog $readmem or Xilinx coe files: github.com/projf/fpgato... * Support 15-bit (RBG555) palette * Use Pillow palette API * Format image output in lines * Generate more compact 16-colour output

Last weekend was the Nova 2025 demoparty in the UK. I worked on a couple of the productions released there. I made a 4Kb Executable Graphics picture "void main". www.pouet.net/prod.php?whi... Since then I've also put a variation of the code up on #shadertoy www.shadertoy.com/view/3fySDR

I'm pondering 15-bit (5 bits per channel) colour for my #FPGA display logic instead of the current 12-bit. I prefer 15 to 16-bit for true greys. 24-bit seems overkill and requires twice the storage. A minor downside is the absence of the human-parseable hex values you get with 12-bit (0xFFC). 🎨