So if you are currently involved with ISA-level decisions about inclusion of any pext/pdep-like instructions: Please consider including SAG/inverse-SAG with bit-reversal of the goats. No matter which of the two implementation methods you are using: All you need to do is not mask the goat bits.

Here is the code: github.com/clairexen/ed... I can't see any obvious reason why that identity should not extend beyond 8-bit units. But I have not actually tested that hypothesis yet.

I have to make a correction regarding ☝️. I've now implemented the Hilewitz-Lee method as well in my edu-sag repository. And it implements the bit-reflecting-SAG as-is. All you have to do is to remove the '&ci' from the data input, thus it's always more area to implement PEXT than bit-reflecting-SAG.

I wrote a reference implementation for a SAG without bit reflection: github.com/clairexen/ed..., and I wrote a parametric SAG core for any bit width: github.com/clairexen/ed...

To have trans friends is to hold candles in the wind. I can’t say if the storm is fate or man-made. I only know I’m losing light.

Yes, I mean the definition of SAG with the mirroring. The non-mirrored version is way more expensive (and IMO actually less desirable anyway). I just wrote this: github.com/clairexen/ed... I've been meaning to write this code for quite some time...

Long time no see, Metalab Vienna

When I was little I wanted a time machine. Now I have (c)PTSD. Beware what you wish for.

I've just posted a reminder on Twitter, that I am now on bsky. Let's make this a doubly linked list: Just in case you wanna see my old Twitter, that I'm not using anymore, here you go: twitter.com/oe1cxw (it'll forward you to "X" but hell no I won't post an X link for this, or call it my "old X" :P)

... and it has a robust CSG engine, described in arxiv.org/abs/2405.12949 (that just got accepted pending minor revisions)

Introducing the Zero to ASIC analog course! youtu.be/wM4cobfjMMQ Don't miss the Black Friday discounts - join the newsletter for $150 off on Friday: zerotoasiccourse.com/newsletter/ Full course details: zerotoasiccourse.com/analog/

After a summer break, our user group meetings have resumed again! In our last call, Katharina CeesaySeitz from ETH Zürich presented her work to detect microarchitectural information leakage via hardware timing side channels. Watch her talk on our Youtube channel! www.youtube.com/watch?v=Kxp-...

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1st post on bluesky!

I've updated my "rules for ready/valid handshakes" to describe both a control implementation I made heavy use of in the past year, and to add discussion on the synchronization operation which underlies ready/valid handshakes, much like ready/valid handshakes underlie AXI4. fpgacpu.ca/fpga/handsha...

Wordle 1,082 3/6* ⬜🟨🟨⬜⬜ 🟨🟩🟩🟨🟩 🟩🟩🟩🟩🟩 ROFL 🤣

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I probably spent way too much time fiddling with those functions today.. But I'm quite happy with what I ended up with. ツ

Wow. ChatGPT knows about my transition and my new name, but only if you know about it as well.

When I was working on RISC-V BitManip I was doing inverse xorshift as a benchmark example. This picture makes a lot of sense ;)

different fields of math are a scam to sell more wikipedia articles. it's all the same math, just rearranged

Gotta post something here as well I guess.. 😅 so here are some selfies I found on my phone that I kinda like 🦋💜✨ #firstpost