I've been working for a long time alongside different folks to spread the word about web standards, how JavaScript is standardized and help improve how responsive we are to the needs of developers. For more @tc39.es lore, read my first post in "What even is Ecma?" www.ryzokuken.dev/blog/about-e...

One of the nice parts of #llvm is that often times you'll find yourself needing to do some sort of non-trivial analysis, but usually there's already a pass for it. Here's how you can reuse a block frequency analysis to make a chess engine 7% faster on #riscv: lukelau.me/2026/01/26/c...

Does LLVM produce slower RISC-V code than GCC? Currently, yes. Can we make LLVM produce faster code? Also, yes! lukelau.me/2025/12/10/c... #llvm #riscv

"How NOT To Program an Out-of-order Vector Processor" slides are public. static.sched.com/hosted_files...

We're looking forward to the RISC-V Summit North America next week where Mikhail Gadelha (one of our compiler engineers) will be presenting "Unlocking 15% More Performance: A Case Study in LLVM Optimization for RISC-V". Be sure to catch his talk next Thurs riscvsummit2025.sched.com/event/28OTp/...

Police have deployed an armoured vehicle in Hong Kong's commercial heart, amidst an ongoing heavy security presence on the 36th anniversary of the Tiananmen Square crackdown. In full: buff.ly/f4hVB50

I'm delighted to see two of @igalia.com's projects for RISE highlighted at the RISC-V Summit Europe. Find out more about our work on both LLVM optimisation and testing/CI on the RISE blog (with more to come in the future!): riseproject.dev/2025/05/08/p... riseproject.dev/2024/10/15/w...

We're looking forward to EuroLLVM next week in Berlin. Be sure to check out talks from my colleague @lukel97.bsky.social and myself on: * Work to further improve RISC-V vector codegen (extending the VL Optimizer), and * Work done with the support of RISE to improve RISC-V LLVM testing.

What if I told you 3DNow! square root recíprocals are defined for negative numbers?... Also the amazing FEX 2503 is out. Read about some of my work and the work of other FEX maintainers' in the release notes: fex-emu.com/FEX-2503/ #fex #igalia #gaming #linux #arm64

Some notes on ccache+LLVM. Summary: if you do a lot of builds across different checkouts/worktrees/builddirs, be sure to set the base_dir option and -DLLVM_USE_RELATIVE_PATHS_IN_DEBUG_INFO=ON muxup.com/2025q1/ccach...

Hello you fine Internet folks, Today's article is on SiFive's P550 microarchitecture. The P550 core is one of the fastest RISC-V cores available currently and is claimed to be comparable to ARM's Cortex A75. Hope y'all enjoy! old.chipsandcheese.com/2025/01/26/i... open.substack.com/pub/chipsand...

New blog post covering the mysterious 10ms startup regression of Node.js on macOS, the journey of investigating the issue with various performance tools, and figuring out the fix (which also helped making the binary smaller). joyeecheung.github.io/blog/2025/01...

A Simple ELF 4zm.org/2024/12/25/a...

After two months of chasing, finally found out what's happening behind this mysterious startup time regression on macOS from Node.js v20.x - it's missing -fvisibility=hidden 😅 (I guess that's what happens when the build configs become dusty enough) github.com/nodejs/node/...

Recently I came across this treatise by Stephen Dolan github.com/ocaml/ocaml/...

Trying to find the slowest possible RISC-V instruction. This single vlse8.v with a stride of 65536 bytes takes 66 million cycles on a Banana Pi F3. That's 0.04 seconds @1.6GHz #risc-v

Here are some slightly tricky RVV mask patterns.