This is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3  μm NMOS process with two interconnect layers. It was one of the first NMOS processes to use separate metal layers for local connections and global signals.

This looks like a matrix. Each one has 128 analog switches. We can do 8x16 analog array with one. So this is actually a analog matrix.

Google has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications. It has been prototyped on a Xilinx Ultrascale Plus FPGA platform. github.com/google-coral...

Leo Moser and myself will be on @crowdsupply.bsky.social 's Teardown Session talking with @helenleigh.bsky.social about @wafer.space this Thursday (3rd October) - youtu.be/tEOmnN8IAjs

FYI : Original electronic diary was invented by a Indian guy known as Satyan Pitroda, alias Sam Pitroda. He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares. www.computerhistory.org/revolution/m...

It was awesome to be on @chrisgammell.bsky.social 's Amp Hour podcast again. Find out more about my latest endeavor to make custom silicon manufacturing accessible and follow @wafer.space and bookmark wafer.space to keep up to date!

Low power math within few clock cycles. Imagine it, then put it into silicon. Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks. Check - t.co/vBGGA2i0uX Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.

SPI-slave device for seven-segment display on TT base board. TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.

ASICs are cool. FPGAs are ❤️. FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social @tinytapeout.com @mattvenn.net @urishaked.bsky.social

Definitely true!

Evening chai is hot enough to give the FPGA a first-class ticket to the electronic afterlife.

When man craves for aesthetics, he craves for God...and good quality probes.

2025 One Hertz Challenge: A 555, but not as we know it

Join me today on the #opensourcesiliconstream to catch up on the latest news and then make a simple quadrature encoder peripheral for the @tinytapeout.com RISC-V competition! www.youtube.com/live/2JTFwLV...

It looks good. Got the power led. Now trying to get it to work as intended.

Booted KianV uLinux from Hirosh on TinyTapeout ASIC.

I fabricated @rebelmike.bsky.social's design for the Tiny Tapeout demo board and then soldered the FPGA. This was my second time soldering a BGA. Had to visit a nearby university to get the X-ray inspection done.

MPW5 up-close and zoomed-in! @tinytapeout.com @mattvenn.net @urishaked.bsky.social

My TT06 board arrived! I don't have a design on this but I intend to try RISC-V SoCs on this. @tinytapeout.com @mattvenn.net

Must read papers for processor design.

I’ve got MicroPython running on TinyQV - my RISC-V SoC that’s on #TinyTapeout 6. Here it is bit banging (from MicroPython!) a rule 30 cellular automaton to an LED matrix display.

I've got my hands on TT06 and I'll be bringing up my Risc-V SoC on #TinyTapeout 6 this evening. I'll mostly post about it over on Fediverse: rebel-lion.uk/@mike/113765...

This is a VAAMAN board. This board features an RK3399 MPU, an Efinix T120 FPGA w/ 112k logic elements, and a high-speed CPU-FPGA link. I'm going to try their Periplex stack, which utilize this link for custom protocol design without relying on MPU capablities.

Turns out that mech keyboards don't last. Back to the classic membrane keyboard!

__cooking xv6-riscv on ecp5__ __Have a nice weekend guys__