Rohan makes RTL on FPGA 🛠️
@rohan-devarc.bsky.social
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📥 28
📝 60
Exploring the ASIC lore. Not your typical lobste. rs link-dumper or book-cover–posting zombie.
pinned post!
Low power math within few clock cycles. Imagine it, then put it into silicon. Made by Vicharak aka
@aksharvastarpara.bsky.social
's team and two FPGA freaks. Check -
t.co/vBGGA2i0uX
Thanks
@mattvenn.net
and
@urishaked.bsky.social
and whole
@tinytapeout.com
team for making this possible.
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3 months ago
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This is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3  μm NMOS process with two interconnect layers. It was one of the first NMOS processes to use separate metal layers for local connections and global signals.
about 1 month ago
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This looks like a matrix. Each one has 128 analog switches. We can do 8x16 analog array with one. So this is actually a analog matrix.
about 1 month ago
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Google has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications. It has been prototyped on a Xilinx Ultrascale Plus FPGA platform.
github.com/google-coral...
about 2 months ago
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reposted by
Rohan makes RTL on FPGA 🛠️
Tim 'mithro' Ansell
2 months ago
Leo Moser and myself will be on
@crowdsupply.bsky.social
's Teardown Session talking with
@helenleigh.bsky.social
about
@wafer.space
this Thursday (3rd October) -
youtu.be/tEOmnN8IAjs
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Teardown Session 56: wafer.space with Tim Ansell
YouTube video by Crowd Supply
https://youtu.be/tEOmnN8IAjs
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FYI : Original electronic diary was invented by a Indian guy known as Satyan Pitroda, alias Sam Pitroda. He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares.
www.computerhistory.org/revolution/m...
add a skeleton here at some point
2 months ago
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reposted by
Rohan makes RTL on FPGA 🛠️
Tim 'mithro' Ansell
2 months ago
It was awesome to be on
@chrisgammell.bsky.social
's Amp Hour podcast again. Find out more about my latest endeavor to make custom silicon manufacturing accessible and follow
@wafer.space
and bookmark
wafer.space
to keep up to date!
add a skeleton here at some point
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Low power math within few clock cycles. Imagine it, then put it into silicon. Made by Vicharak aka
@aksharvastarpara.bsky.social
's team and two FPGA freaks. Check -
t.co/vBGGA2i0uX
Thanks
@mattvenn.net
and
@urishaked.bsky.social
and whole
@tinytapeout.com
team for making this possible.
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3 months ago
1
13
6
SPI-slave device for seven-segment display on TT base board. TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.
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4 months ago
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ASICs are cool. FPGAs are ❤️. FPGA brother to tinytapeout ASIC by Michael Bell aka
@rebelmike.bsky.social
@tinytapeout.com
@mattvenn.net
@urishaked.bsky.social
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4 months ago
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Definitely true!
4 months ago
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Evening chai is hot enough to give the FPGA a first-class ticket to the electronic afterlife.
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4 months ago
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When man craves for aesthetics, he craves for God...and good quality probes.
4 months ago
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reposted by
Rohan makes RTL on FPGA 🛠️
Hackaday
5 months ago
2025 One Hertz Challenge: A 555, but not as we know it
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2025 One Hertz Challenge: A 555, but not as we know it
Hackaday Article
https://hackaday.com/2025/07/22/2025-one-hertz-challenge-a-555-but-not-as-we-know-it/
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reposted by
Rohan makes RTL on FPGA 🛠️
Matt Venn
5 months ago
Join me today on the
#opensourcesiliconstream
to catch up on the latest news and then make a simple quadrature encoder peripheral for the
@tinytapeout.com
RISC-V competition!
www.youtube.com/live/2JTFwLV...
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Open Source Silicon Stream #18 - Quadrature Encoder RISC-V peripheral
Join the stream for latest news in open source silicon, followed by some hacking on a quadrature encoder peripheral for the Tiny Tapeout RISC-V competition. https://docs.google.com/document/d/197sZCd...
https://www.youtube.com/live/2JTFwLVpZSE
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It looks good. Got the power led. Now trying to get it to work as intended.
add a skeleton here at some point
5 months ago
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Booted KianV uLinux from Hirosh on TinyTapeout ASIC.
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5 months ago
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I fabricated
@rebelmike.bsky.social
's design for the Tiny Tapeout demo board and then soldered the FPGA. This was my second time soldering a BGA. Had to visit a nearby university to get the X-ray inspection done.
5 months ago
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MPW5 up-close and zoomed-in!
@tinytapeout.com
@mattvenn.net
@urishaked.bsky.social
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5 months ago
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My TT06 board arrived! I don't have a design on this but I intend to try RISC-V SoCs on this.
@tinytapeout.com
@mattvenn.net
5 months ago
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Must read papers for processor design.
11 months ago
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reposted by
Rohan makes RTL on FPGA 🛠️
Mike Bell
11 months ago
I’ve got MicroPython running on TinyQV - my RISC-V SoC that’s on
#TinyTapeout
6. Here it is bit banging (from MicroPython!) a rule 30 cellular automaton to an LED matrix display.
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reposted by
Rohan makes RTL on FPGA 🛠️
Mike Bell
11 months ago
I've got my hands on TT06 and I'll be bringing up my Risc-V SoC on
#TinyTapeout
6 this evening. I'll mostly post about it over on Fediverse:
rebel-lion.uk/@mike/113765...
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Mike Bell (@
[email protected]
)
Attached: 1 image Finally got my hands on #TinyTapeout 06! I’ve been really looking forward to this, it has my RISC-V RV32EC SoC, which (assuming it works) should be much faster and more flexible tha...
https://rebel-lion.uk/@mike/113765315909779729
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This is a VAAMAN board. This board features an RK3399 MPU, an Efinix T120 FPGA w/ 112k logic elements, and a high-speed CPU-FPGA link. I'm going to try their Periplex stack, which utilize this link for custom protocol design without relying on MPU capablities.
11 months ago
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Turns out that mech keyboards don't last. Back to the classic membrane keyboard!
11 months ago
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__cooking xv6-riscv on ecp5__ __Have a nice weekend guys__
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11 months ago
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