Li Lu, Jianan Wen, Milos Krstic: FsimNNs: An Open-Source Graph Neural Network Platform for SEU Simulation-based Fault Injection https://arxiv.org/abs/2511.09131 https://arxiv.org/pdf/2511.09131 https://arxiv.org/html/2511.09131

Eren Kurshan, Yuan Xie, Paul Franzon: 3D Guard-Layer: An Integrated Agentic AI Safety System for Edge Artificial Intelligence https://arxiv.org/abs/2511.08842 https://arxiv.org/pdf/2511.08842 https://arxiv.org/html/2511.08842

[2025-11-13 Thu (UTC), 2 new articles found for csAR Hardware Architecture]

Zhuoheng Ran, Chong Wu, Renjie Xu, Maolin Che, Hong Yan: UniFormer: Unified and Efficient Transformer for Reasoning Across General and Custom Computing https://arxiv.org/abs/2511.08135 https://arxiv.org/pdf/2511.08135 https://arxiv.org/html/2511.08135

Gina Sohn, Genghan Zhang, Konstantin Hossfeld, Jungwoo Kim, Nathan Sobotka, Nathan Zhang, Olivia Hsu, Kunle Olukotun: Streaming Tensor Program: A streaming abstraction for dynamic parallelism https://arxiv.org/abs/2511.07776 https://arxiv.org/pdf/2511.07776 https://arxiv.org/html/2511.07776

Xiaomeng Yang, Jian Gao, Yanzhi Wang, Xuan Zhang: ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddings https://arxiv.org/abs/2511.07658 https://arxiv.org/pdf/2511.07658 https://arxiv.org/html/2511.07658

Zhenxiao Fu, Chen Fan, Lei Jiang: CO2-Meter: A Comprehensive Carbon Footprint Estimator for LLMs on Edge Devices https://arxiv.org/abs/2511.08575 https://arxiv.org/pdf/2511.08575 https://arxiv.org/html/2511.08575

Xingyu Liu, Jiawei Liang, Yipu Zhang, Linfeng Du, Chaofang Ma, Hui Yu, Jiang Xu, Wei Zhang: DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator https://arxiv.org/abs/2511.08395 https://arxiv.org/pdf/2511.08395 https://arxiv.org/html/2511.08395

Mingkai Miao, Jianheng Tang, Guangyu Hu, Hongce Zhang: BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learning https://arxiv.org/abs/2511.08315 https://arxiv.org/pdf/2511.08315 https://arxiv.org/html/2511.08315

Shi, Lin, Wang, Xu, Kai, Lai, Gao, Xue, Yuan, Qian, Zhou: Re$^{\text{2}}$MaP: Macro Placement by Recursively Prototyping and Packing Tree-based Relocating https://arxiv.org/abs/2511.08054 https://arxiv.org/pdf/2511.08054 https://arxiv.org/html/2511.08054

Simei Yang, Xinyu Shi, Lu Zhao, Yunyu Ling, Quanjun Wang, Francky Catthoor: PIMfused: Near-Bank DRAM-PIM with Fused-layer Dataflow for CNN Data Transfer Optimization https://arxiv.org/abs/2511.07985 https://arxiv.org/pdf/2511.07985 https://arxiv.org/html/2511.07985

Fu, Zhou, Ye, Duan, Huang, Wei, Guo, Li, Chen: FractalCloud: A Fractal-Inspired Architecture for Efficient Large-Scale Point Cloud Processing https://arxiv.org/abs/2511.07665 https://arxiv.org/pdf/2511.07665 https://arxiv.org/html/2511.07665

[2025-11-12 Wed (UTC), 6 new articles found for csAR Hardware Architecture]

Zhaohui Yang, Dawei Ding, Qi Ye, Cupjin Huang, Jianxin Chen, Yuan Xie: ReQISC: A Reconfigurable Quantum Computer Microarchitecture and Compiler Co-Design https://arxiv.org/abs/2511.06746 https://arxiv.org/pdf/2511.06746 https://arxiv.org/html/2511.06746

Suchita Pati, Mahzabeen Islam, Shaizeen Aga, Mohamed Assem Ibrahim: DMA Collectives for Efficient ML Communication Offloads https://arxiv.org/abs/2511.06605 https://arxiv.org/pdf/2511.06605 https://arxiv.org/html/2511.06605

Michael Jaemin Kim, Seungmin Baek, Jumin Kim, Hwayong Nam, Nam Sung Kim, Jung Ho Ahn: SoK: Systematizing a Decade of Architectural RowHammer Defenses Through the Lens of Streaming Algorithms https://arxiv.org/abs/2511.06192 https://arxiv.org/pdf/2511.06192 https://arxiv.org/html/2511.06192

Theofanis Vergos, Polykarpos Vergos, Mehdi B. Tahoori, Georgios Zervakis: Bespoke Co-processor for Energy-Efficient Health Monitoring on RISC-V-based Flexible Wearables https://arxiv.org/abs/2511.05985 https://arxiv.org/pdf/2511.05985 https://arxiv.org/html/2511.05985

Yihang Qiu, Zengrong Huang, Simin Tao, Hongda Zhang, Weiguo Li, Xinhua Lai, Rui Wang, Weiqiang Wang, Xingquan Li: AiEDA: An Open-Source AI-Aided Design Library for Design-to-Vector https://arxiv.org/abs/2511.05823 https://arxiv.org/pdf/2511.05823 https://arxiv.org/html/2511.05823

Justin Williams, Kishor Datta Gupta, Roy George, Mrinmoy Sarkar: Lite VLA: Efficient Vision-Language-Action Control on CPU-Bound Edge Robots https://arxiv.org/abs/2511.05642 https://arxiv.org/pdf/2511.05642 https://arxiv.org/html/2511.05642

Benjamin Hawks, et al.: wa-hls4ml: A Benchmark and Surrogate Models for hls4ml Resource and Latency Estimation https://arxiv.org/abs/2511.05615 https://arxiv.org/pdf/2511.05615 https://arxiv.org/html/2511.05615

Eun-Su Cho, Jongin Choi, Jeongmin Jin, Jae-Jin Lee, Woojoo Lee: FiCABU: A Fisher-Based, Context-Adaptive Machine Unlearning Processor for Edge AI https://arxiv.org/abs/2511.05605 https://arxiv.org/pdf/2511.05605 https://arxiv.org/html/2511.05605

Arya Parameshwara, Santosh Hanamappa Mokashi: FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices https://arxiv.org/abs/2511.06955 https://arxiv.org/pdf/2511.06955 https://arxiv.org/html/2511.06955

Ilias Papalamprou, Dimosthenis Masouros, Ioannis Loudaros, Francky Catthoor, Dimitrios Soudris: Optimizing GEMM for Energy and Performance on Versal ACAP Architectures https://arxiv.org/abs/2511.06907 https://arxiv.org/pdf/2511.06907 https://arxiv.org/html/2511.06907

Yuzong Chen, Chao Fang, Xilai Dai, Yuheng Wu, Thierry Tambe, Marian Verhelst, Mohamed S. Abdelfattah: P3-LLM: An Integrated NPU-PIM Accelerator for LLM Inference Using Hybrid Numerical Formats https://arxiv.org/abs/2511.06838 https://arxiv.org/pdf/2511.06838 https://arxiv.org/html/2511.06838

Tamoghno Das, Khanh Phan Vu, Hanning Chen, Hyunwoo Oh, Mohsen Imani: ASTER: Attention-based Spiking Transformer Engine for Event-driven Reasoning https://arxiv.org/abs/2511.06770 https://arxiv.org/pdf/2511.06770 https://arxiv.org/html/2511.06770

Arsalan Ali Malik, John Buchanan, Aydin Aysu: Preemption-Enhanced Benchmark Suite for FPGAs https://arxiv.org/abs/2511.06736 https://arxiv.org/pdf/2511.06736 https://arxiv.org/html/2511.06736

Sangun Choi, Yunho Oh: EONSim: An NPU Simulator for On-Chip Memory and Embedding Vector Operations https://arxiv.org/abs/2511.06679 https://arxiv.org/pdf/2511.06679 https://arxiv.org/html/2511.06679

Arnab A Purkayastha, Jay Tharwani, Shobhit Aggarwal: FPGA or GPU? Analyzing comparative research for application-specific guidance https://arxiv.org/abs/2511.06565 https://arxiv.org/pdf/2511.06565 https://arxiv.org/html/2511.06565

Akshay Revankar, Charan Renganathan, Sartaj Wariah: Offloading Data Center Tax https://arxiv.org/abs/2511.06558 https://arxiv.org/pdf/2511.06558 https://arxiv.org/html/2511.06558

Cuyckens, Yi, Geens, Dumoulin, Wiesner, Fang, Verhelst: Precision-Scalable Microscaling Datapaths with Optimized Reduction Tree for Efficient NPU Integration https://arxiv.org/abs/2511.06313 https://arxiv.org/pdf/2511.06313 https://arxiv.org/html/2511.06313

Omin Kwon, Kyungjun Oh, Jaeyong Lee, Myungsuk Kim, Jihong Kim: STAR: Improving Lifetime and Performance of High-Capacity Modern SSDs Using State-Aware Randomizer https://arxiv.org/abs/2511.06249 https://arxiv.org/pdf/2511.06249 https://arxiv.org/html/2511.06249

Zifan He, Shengyu Ye, Rui Ma, Yang Wang, Jason Cong: LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAs https://arxiv.org/abs/2511.06174 https://arxiv.org/pdf/2511.06174 https://arxiv.org/html/2511.06174

Park, Park, Kim, Yune, Han, Nam: Delay Time Characterization on FPGA: A Low Nonlinearity, Picosecond Resolution Time-to-Digital Converter on 16-nm FPGA using Bin Sequence Calibration https://arxiv.org/abs/2511.05583 https://arxiv.org/pdf/2511.05583 https://arxiv.org/html/2511.05583

Zhichao Chen, Puneet Gupta: YAP+: Pad-Layout-Aware Yield Modeling and Simulation for Hybrid Bonding https://arxiv.org/abs/2511.05506 https://arxiv.org/pdf/2511.05506 https://arxiv.org/html/2511.05506

Stef Cuyckens, Ryan Antonio, Chao Fang, Marian Verhelst: iEEG Seizure Detection with a Sparse Hyperdimensional Computing Accelerator https://arxiv.org/abs/2511.05503 https://arxiv.org/pdf/2511.05503 https://arxiv.org/html/2511.05503

Varun Rajesh, et al.: Production-Grade Local LLM Inference on Apple Silicon: A Comparative Study of MLX, MLC-LLM, Ollama, llama.cpp, and PyTorch MPS https://arxiv.org/abs/2511.05502 https://arxiv.org/pdf/2511.05502 https://arxiv.org/html/2511.05502

[2025-11-11 Tue (UTC), 15 new articles found for csAR Hardware Architecture]

Varun Manjunath, Pranav Ramesh, Gopalakrishnan Srinivasan: NeuroFlex: Column-Exact ANN-SNN Co-Execution Accelerator with Cost-Guided Scheduling https://arxiv.org/abs/2511.05215 https://arxiv.org/pdf/2511.05215 https://arxiv.org/html/2511.05215

Xingzhi Zhang, Buyi Lv, Yimin Lu, Kai Bu: PhantomFetch: Obfuscating Loads against Prefetcher Side-Channel Attacks https://arxiv.org/abs/2511.05110 https://arxiv.org/pdf/2511.05110 https://arxiv.org/html/2511.05110

Liu Jiang, Zerui Bao, Shiqi Sheng, Di Zhu: SLOFetch: Compressed-Hierarchical Instruction Prefetching for Cloud Microservices https://arxiv.org/abs/2511.04774 https://arxiv.org/pdf/2511.04774 https://arxiv.org/html/2511.04774

Lacouture, Zhang, Sharma, Siracusa, Kjolstad, Olukotun, Hsu: FuseFlow: A Fusion-Centric Compilation Framework for Sparse Deep Learning on Streaming Dataflow https://arxiv.org/abs/2511.04768 https://arxiv.org/pdf/2511.04768 https://arxiv.org/html/2511.04768

Maximilian Kirschner, Konstantin Dudzik, Ben Krusekamp, J\"urgen Becker: MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference https://arxiv.org/abs/2511.05321 https://arxiv.org/pdf/2511.05321 https://arxiv.org/html/2511.05321

Matheus Farias, Wanghley Martins, H. T. Kung: MDM: Manhattan Distance Mapping of DNN Weights for Parasitic-Resistance-Resilient Memristive Crossbars https://arxiv.org/abs/2511.04798 https://arxiv.org/pdf/2511.04798 https://arxiv.org/html/2511.04798

Mahek Desai, Rowena Quinn, Marjan Asadinia: SMART-WRITE: Adaptive Learning-based Write Energy Optimization for Phase Change Memory https://arxiv.org/abs/2511.04713 https://arxiv.org/pdf/2511.04713 https://arxiv.org/html/2511.04713

Teona Bagashvili, Tarikul Islam Papon, Subhadeep Sarkar, Manos Athanassoulis: Eliminating the Hidden Cost of Zone Management in ZNS SSDs https://arxiv.org/abs/2511.04687 https://arxiv.org/pdf/2511.04687 https://arxiv.org/html/2511.04687

Yuchao Qin, Anjunyi Fan, Bonan Yan: RAS: A Bit-Exact rANS Accelerator For High-Performance Neural Lossless Compression https://arxiv.org/abs/2511.04684 https://arxiv.org/pdf/2511.04684 https://arxiv.org/html/2511.04684

Eleni Bougioukou, Theodore Antonakopoulos: Efficient Deployment of CNN Models on Multiple In-Memory Computing Units https://arxiv.org/abs/2511.04682 https://arxiv.org/pdf/2511.04682 https://arxiv.org/html/2511.04682

[2025-11-10 Mon (UTC), 6 new articles found for csAR Hardware Architecture]

Hyunseok Kwak, Kyeongwon Lee, Jae-Jin Lee, Woojoo Lee: LoRA-Edge: Tensor-Train-Assisted LoRA for Practical CNN Fine-Tuning on Edge Devices https://arxiv.org/abs/2511.03765 https://arxiv.org/pdf/2511.03765 https://arxiv.org/html/2511.03765

Moreno, et al.: Scalable and Efficient Intra- and Inter-node Interconnection Networks for Post-Exascale Supercomputers and Data centers https://arxiv.org/abs/2511.04677 https://arxiv.org/pdf/2511.04677 https://arxiv.org/html/2511.04677