For its announcement at CES, AMD provided a rendering of a Ryzen 9000X3D with two CCDs, each with 3D V-Cache, as marketing material. The same rendering had already been used for the Ryzen 9 9950X3D. Nevertheless, some interpreted this as a hint at the Ryzen 9 9950X3D2.

Since there appears to be a demand for DDR3 in certain markets, I have opened my old treasure chest. Any offers?

Those small silicon slices that, are visible left and right from the two IODs of Venice, must serve a purpose of signal integrity, right?

MSI GeForce RTX 5090 32G Lightning Z - OC BIOS: 800 W - Extreme BIOS: 1,000 W - 8" Display - 40 phase power stages - full copper, full cover water block www.hardwareluxx.de/index.php/ne...

der8auer shows the inner guts (PCB and so on) of NVIDIA’s secret TITAN ADA prototype. www.youtube.com/watch?v=c3Iy...

An AI boom makes Boom Supersonic building #Superpower gas turbines, which could provide the company with a solid economic basis for the development of the aircraft. But I also want to question the installation and supply of gigantic data centers in this form.

DNP achieves 10 nm line-pattern resolution on nanoimprint lithography (NIL) template. According to DNP NIL can replace a portion of the EUV process. The newest template uses Self-Aligned Double Patterning (SADP), which doubles pattern density. www.global.dnp/news/detail/...

Nowadays, they are collector's items.

This is really a bad sign for consumers and might lead to even higher prices in the near future – even though Micron will still supply the OEM market. AI is sucking up everything by the look of things. investors.micron.com/news-release...

.@awscloud Trainium3 - 3 nm - 144 GB HBM3E - 4.9 TB/s Trn3 UltraServers - up to 144 Trainium3 - 20.7 TB HBM3E - 706 TB/s - NeuronSwitch-v1 - an all-to-all fabric

The solvents in some thermal pads seem to dissolve the printing on the GDDR7 memory chips. For a moment, I thought the chips themselves were sticking to them.

GUC on Integrated Voltage Regulator (IVR) integrated in TSMCs CoWoS-L interposer GUCs IVR Spec: - Dual-phase IVR per xPU core or a cluster - Input voltage: 1.8V - Programmable output voltage: 0.5V-1.0V - Efficiency: 85% - Power density: 3W/mm2 - Can use MIMs and DTCs

32 GB DDR5-6000 CL30 just 55,998.99 Euros. It could be a bargain at some point.

TSMC on HBM4 and C-HBM4E HBM4: - N12 base die - 0.8 V Vdd C-HBM4E: - N3P base die - 0.75 V Vdd - memory controller inside base die www.hardwareluxx.de/index.php/ne...

TSMC Advanced Logic Technology Roadmap from OIP Forum Europe – no surprises here. N2P starts in H1 2026. A16 with SPR in H2 2026. Continuous speed and power scaling, but power/speed shows some slowdown, doesn't it? www.hardwareluxx.de/index.php/ne...

Things are heating up: TSMC formally sues ex-SVP over alleged transfer of secrets to Intel www.digitimes.com/news/a202511...

I like that kind of stuff. Thats a CFD of the upcoming Artemis II mission that was run on the Cabeus supercomputer. NASA will add two strakes to the core stage of SLS, that will smooth vibrations induced by airflow during ascent - all simulated! www.youtube.com/watch?v=oJqk...

FP64 is not dead. Do you hear me NVIDIA? Emulated FP64? Ozaki scheme? Please discuss!

Microsoft Cobalt 200 - TSMC 3 nm - two chiplets with custom HB interconnect - 132 cores (Armv9.2), 66 per chiplet - 3 MB private L2$ - 192 MB L3$ - 12 memory channels - per core DVFS www.hardwareluxx.de/index.php/ne...

Our server needs an upgrade.

The DDR5 market goes crazy right now. On the German market, memory kits are sometimes twice as expensive as they were when they were launched a few months ago (or not available at all). This has also led to some memory manufacturers deciding not to launch new series at all.

IBM Quantum Loon and Quantum Nighthawk that are being fabricated at NY CREATES' Albany NanoTech Complex on the 300 mm wafer line.

"Tachyum Unveils 2nm Prodigy with 21x Higher AI Rack Performance than the Nvidia Rubin Ultra" - 1,024 64-bit cores - up to 6 GHz - 1 GB L2+L3$ - 24x DDR5-17600 - 48 TB per socket - 128 lanes of PCIe 7.0 - 1,600 W TDP But surely ...

A good addition to the lineup? AMD did today release the Ryzen 5 7500X3D, which is a very efficient six core CPU, but overpriced compared to the Ryzen 5 7600X3D. We are also not sure whether six cores will still be future-proof in 2025. www.hardwareluxx.de/index.php/ar...

My piece on the Financial Analyst Day by AMD yesterday covering the Zen, Epyc and Instinct roadmaps plus near future product releases and details on them. www.hardwareluxx.de/index.php/ne...

Needed to disassemble a GeForce RTX 5090 for a reason. The reason is stupid 🤪

My colleague visited on of the worldwide five pop-up stores by Intel that are or will be located in Munich, Paris, London, New York and Soul. www.hardwareluxx.de/index.php/ne...

There is a company making billions per quarter, but doing an increasingly bad job in terms of PR. They are giving a lot of infos, also the (in my opinion) important ones, but are holding back on basic stuff like photos of these announcements or are not providing them willingly.

This is #Discovery, the next-gen supercomputer run by ORNL and build by HPE. Discovery will use AMD Instinct MI430X accelerators and Epyc "Venice" CPUs. www.hardwareluxx.de/index.php/ne...

Single die and dual die implementation of the Maverick-2 by @nextsilicon.com. Single die package is used with the PCIe card while die dual die package sits on the OAM module.

Die shot from @nextsilicon.com. But this can't be the Maverick-2, because the aspect ratios look a bit strange, or rather, the HBM PHYs are positioned on the long side here. Or am I wrong? It's been a long week, so apologies in advance!

I‘m kind of shocked that people within the business thought that TSMC manufacturing wafer with Blackwell GPUs in Arizona are giving NVIDIA the ability to do all the silicon related manufacturing independent from Taiwan 🇹🇼

The two Broadcom #Tomahawk 6 102.4T switch chip in two package variants: Tomahawk 6 112G SerDes (bigger package) Tomahawk 6 224G SerDes (smaller package) Source: @servethehome.com.web.brid.gy

Researchers at KAUST have stacked six transistors (OxTs and OrTs in an alternating fashion) on top of each other. These stacks consist of 41 layers, fabricated using a 40-step lithography process, each containing 100 devices.

OpenAI and Tachyum announce strategic partnership to deploy 10 Quadrillion Watts of Compute Power without deploying any actual Chip made by Tachyum.

TSMC Revenue by Node as of Q3 2025. We should see N2 emerging by Q1 2026 in this graph.

Apple M5 - 4x Performance Core - 6x Efficiency Core - +15% nT Performance - +45% higher GPU Performance - 153 GB/s Memory Interface - 3 nm Process

Intel just announced Crescent Island. Crescent Island is a new Intel Data Center GPU offering that will arrive in the second half of 2026. Knows features: - air-cooled - Xe3P microarchitecture - 160 GB of LPDDR5X Looks like a competitor to Rubin CPX and token optimized XPUs.

At 2025 OCP Global Summit AMD shows their Helios rack-scale solution. These are liquid-cooled, 72-GPU racks powering AMD Instinct MI450 Series GPUs, AMD EPYC CPUs (Venice) and do feature integrated UALoE scale-up connectivity.

Interesting project by der8auer: Spray cooling with Novec 7000. Acceptable idle temperatures, nothing more. Just a POC. But, spray cooling was used with the Cray X1 supercomputer. Small holes in the heatspreader sprayed directly onto the small chips, and the gas was returned.

It's official! OpenAI and Broadcom announce strategic collaboration to deploy 10 GW of OpenAI-designed AI accelerators. OpenAI and Broadcom have signed a term sheet to deploy racks incorporating the AI accelerators and Broadcom networking solutions.

One of the slides that shows the potential of #PantherLake the best. 4P+8E+4LPE cores on par with 4P+4LPE (Lunar Lake) and better than 6P+8E+2LPE (Arrow Lake-H), where the allocation of those LPE cores had it’s hurdles.

Robinson Lake reference design for embedded/robotics #PantherLake solutions. The CPU is rated for an extended temperature range of -40 °C to 105 °C. The memory chips are labeled with 4ZC42 DBFVB from Micron. #IntelTechTour

This is a #Intel18A wafer with #PantherLake compute tiles. I did a quick annotation (see 2nd picture attached).

I had the opportunity to visit Intel's #Fab52 at the Ocotillo campus in Chandler, Arizona. This is where Intel manufactures its chips in #Intel18A. In this report, I attempt to convey the enormous dimensions and challenges involved. #IntelTechTour www.hardwareluxx.de/index.php/ne...

A switch from #Crestmont to #Darkmont and thus a significant leap in CPU performance, but still platform-compatible and technically impressive with #Intel18A + #FoverosDirect3D. Intel provides further details on #ClearwaterForest, also known as #Xeon6+. www.hardwareluxx.de/index.php/ne...

Based on todays details about #PantherLake and #ClearwaterForest, we took another look at the details of #Intel18A, #PowerVia (including Omni MIM), #RibbonFET, and #Foveros. #IntelTechTour www.hardwareluxx.de/index.php/ne...

New (revised) E- and P-Cores, a new Xe3 GPU, significantly more efficient NPU 5 and #PantherLake in three chip configurations with a mix and match of #Intel18, #Intel3 and TSMC N6 and N3E — today we take a look at the details of Intel's upcoming CPU gen. www.hardwareluxx.de/index.php/ar...

300 mm GaN-on-Si wafer from Aixtron as presented by imec

According to Prashanth Aprameyan, GM for Intel 18A & Intel 3 at Intel Foundry Services, Intel 18A-P will enter HVM by the end of 2026. This is following what Intels own roadmaps are showing. My question is: Which product(s) will use Intel 18A-P?