if this 100% FPGA demo is passing for a shader, that’s probably my cue to release it. this is an early demo of my own work to replicate the 3dfx sst-1 pipeline in systemverilog. there is a non-canon geometry engine driving it from within the FPGA for kicks.

After Dark’s Satori screensaver on some LEDs. Algorithm cribbed from github.com/jlieske/fluere

#PicoGUS can now emulate Sound Blaster 16 with the newly released firmware v4.0.0! Other changes include CD-ROM speed and reliability improvements, GUS mode improvements, and more. Check the full changelog and download the release at github.com/polpo/picogu...

now with more colors (combinations of channels)

recreated an old LED display hack of mine. each color channel is its own world of conway's life. instead of erasing cells, phosphor is emulated. there are snakes, if a snake from one color channel encounters a cell from another, it grows and changes the cell color.

Thinking Machines' CM-5's "Random and Pleasing" activity mode 7 distributed across 512x128 pixels as a backdrop for my soldering bench, cribbed from gist.github.com/zeroeth/c1e8...

MiSTVGA now works with a much smaller FPGA using SDRAM. Slightly modified Terasic DE0-Nano.

Please enjoy a couple of the ATi cofounders talking about early board development www.youtube.com/watch?v=tajO...

with artemis ii my code has left earth orbit, but so has candy crush

The PicoGUS in SB16 mode works in Windows XP

nothing so cathartic as repair

I cared so much about politics and then realized the material result of all of that caring and it burned me out. So I care about those I know who are impacted by politics, instead.

That’s an herbivore.

ez baking

Zen

Announcing the second Tiny Tapeout demoscene competition! Free silicon space for all entrants! tinytapeout.com/competitions...

pareto principled framing

First, some fun with a reverse engineered FPGA board. Different bus.

My SystemVerilog 3dfx design goes beyond simulation, and includes stippling, per-LOD addressing,, multitexturing, and a display controller - validated on real hardware.

Repaired.

Repairing.

github.com/ianhan/MiSTVGA I ported the ao486 VGA core to run on my PCI FPGA setup - works with a real PC, runs Quake/DOOM/Keen.

When I said #PicoGUS wasn’t being left behind, I wasnt joking! This is a regular ol’ PicoGUS being a Sound Blaster 16, detected and working in Windows 98:

I can confirm tubetime's schematic capture of the MCGA chipset is good enough to use as a reference.

PC Magazine’s advice for acquiring the EGA TRM from IBM (1986)

this framebuffer is slowly being drawn by something under simulation (verilator + bochs) and in this case it's not my ip. it belonged to number nine visual technology. this is the number nine "ticket to ride iv" vga/3d ip that was open sourced as "GPLGPU" - as exercised by bootloader code.

probe_passive now supports pinfiles for grabbing the current state of named pins over JTAG.

Stranger things.

My PCI MDA got weirder.

TubeTime’s monochrome display adapter core ported to my PCI FPGA VGA passthrough board. Maybe the first PCI MDA card. Full intensity is white, everything else is bitwise abuse of a rainbow pattern generator.

more of the 3D pipeline online

artifacting

have some glitch art.

I have no way to convey how strange it is for me to be able to see this from an FPGA.

Given a JTAG chain, walk the chain and map out the connections between all chips on the chain for which you have BSDL files (in this case, a configuration/flash mgmt CPLD and the FPGA it configures).

The OpenOCD backend expands support past Altera FPGAs (and FPGAs in general).

I’m building FPGA/PCB RE tools that actively probe a JTAG chain via OpenOCD or Altera’s AJI API using BSDL files. This script walks the chain, placing one device at a time into EXTEST, then samples boundary scan data long enough to identify pins carrying active clock signals.

very serious work is happening right now (sound on)

3,488 triangle edition of the Utah teapot, environment mapped by a hardware geometry engine through my recreation of the SST-1 fixed function pipeline. Important note: because it is the Utah teapot, the bottom is missing. Wouldn't be right to add it. 100% FPGA hardware. Entirely SystemVerilog.

one more use of the geometry engine, but first under simulation

the fjord torus’ geometry engine was a fun detour for debugging. next stop: bus w/software doing the driving

made a gif for the github page

hp color recovery doing 1080p44 out of a 2MB sram

decided to become a not-quite-anon after reading pastebin.com/Ft7P5m9F

Been chewing on what to put in README․md with AI in the loop. Presenting the AI CODING ADVISORY SYSTEM. Useful labels for whatever the heck I just built.

timing glitch art (free to a good home)

I don’t have the BRAM for a depth buffer so it’s time to get the memory controller up and running for this fjord torus. 100% FPGA logic 3D pipeline, no CPU.

the 3d rast pipeline is a tools-assisted speedrun. the combo of claude code + codex is turning what would have taken years into months.