Given a JTAG chain, walk the chain and map out the connections between all chips on the chain for which you have BSDL files (in this case, a configuration/flash mgmt CPLD and the FPGA it configures).

The OpenOCD backend expands support past Altera FPGAs (and FPGAs in general).

I’m building FPGA/PCB RE tools that actively probe a JTAG chain via OpenOCD or Altera’s AJI API using BSDL files. This script walks the chain, placing one device at a time into EXTEST, then samples boundary scan data long enough to identify pins carrying active clock signals.

very serious work is happening right now (sound on)

3,488 triangle edition of the Utah teapot, environment mapped by a hardware geometry engine through my recreation of the SST-1 fixed function pipeline. Important note: because it is the Utah teapot, the bottom is missing. Wouldn't be right to add it. 100% FPGA hardware. Entirely SystemVerilog.

one more use of the geometry engine, but first under simulation

the fjord torus’ geometry engine was a fun detour for debugging. next stop: bus w/software doing the driving

made a gif for the github page

hp color recovery doing 1080p44 out of a 2MB sram

decided to become a not-quite-anon after reading pastebin.com/Ft7P5m9F

Been chewing on what to put in README․md with AI in the loop. Presenting the AI CODING ADVISORY SYSTEM. Useful labels for whatever the heck I just built.

timing glitch art (free to a good home)

I don’t have the BRAM for a depth buffer so it’s time to get the memory controller up and running for this fjord torus. 100% FPGA logic 3D pipeline, no CPU.

the 3d rast pipeline is a tools-assisted speedrun. the combo of claude code + codex is turning what would have taken years into months.

come warm yourself by my 100% FPGA logic 3D rasterization pipeline… while the geometry engine (also logic) cubes.

First light on real hardware. I will call it what it is when I decide it is.

there's a special disease programmers get. basically, they build a lot of stuff and every time they fight with some framework. eventually they're like "I'm gonna write my own damn framework" and then they write their own framework that innovates on the frustration.

recently I rubber-ducky debugged something with claude code and then I used it to reconstruct some algorithms from expired patents so I could understand them. now it creates test benches, test harnesses, and does grunt work. we're not going back.

you can guess what I'm working on. you'll probably be right.

Got deep color (12 bits per channel) from the Terasic FMC-HDMI with the Altera Stratix V Advanced Systems Development Kit.

whomever wrote dvi_tx/dvi_tx_tmds_enc for bit banged dvi (mike field?): thanks. modified it to encode dvi for altera's phy ip to use the hssi tx blocks on the arria v gx kit.

binge-coding with claude. reproduced the algorithms for hp color recovery from expired patents.

if I have to stare at it, it should probably look nice

this claude guy does fine work🤔

emulation progress

random realization: it makes sense that the option rom header signature is 0x55 0xAA for the same reason those values are used when doing a hardware detection knock on the AT bus, or, recently, memory controller training: every other bit is set. 0x55 = 01010101 0xAA = 10101010

PC-FX GA GMAKER SDK Documentation (English Translation): github.com/ianhan/gmake...

chonk

@tubetime.bsky.social did you toss your mcga documentation somewhere?

my leenoochs box has a status display sitting off an FPGA that implements a framebuffer (for which it has a tinydrm driver). the stats are from a modified version of btop to which I've added claude usage.

something 9-ish coming

dual cpu abit bp6 running beos with bebox style blinkenlights on an x86 over smbus.

another piece in place: wrote a beos driver for the piix4 chipset to do one thing and one thing only: pass the stats - x86 with blinkenlights, my first beos driver. rip be, inc.

two celerons walked into a bar

Turkey day fun: You can interface I2C devices with a PC’s SMBUS as long as there are no address conflicts. This is an SSD1306 based 128x32 monochrome OLED on an abit bp6 motherboard (running T2 SDE Linux). SMBCON pinout and gist follow. It is device ‘3c’ here.

Are you ready for #PicoIDE? It seems to be telling me it's ready. Coming soon: ATAPI optical disc emulation and IDE hard drive emulation. picoide.com

Starting this December I'll be traveling for about a year - the goal is to bounce between continents and chase good food/stories/experiences. Recommendations welcome.

Google PR men: the web is thriving Google in court, where it is illegal to lie: the web is in decline

The masses were robbed of bicolor dot matrix vacuum fluorescent displays.

Thinking about attending Chaos Communication Congress (CCC) 39 in December.

I think I'm gonna bury myself in a new PCB project for the next couple weeks and just try to pretend that everything else is gonna be fine. Maybe I'll come up with something fun.

Weird retro computing find: a Dream SAM9203 based ISA card with the GMS93160x sample ROMs that got them in hot water with Roland. I think it’s a reference design, labeled DREAM 92PCGM. Descent II approves. Photo in reply is from seller - I removed the stray component lead before trying the card out.

This is a pretty good example of what it's like to try an LLM right now. Generating a table of JTAG instruction registers and their use based on the Verilog and interrupting itself to advertise a web development suite instead.

If my network redundancy is working correctly I should be posting this through SPACE†

That gradient test pattern was generated during scanout. Took a few days but I finally got the trace delay settings close enough to scan a framebuffer out of DDR SDRAM. Now all board features are working/in use.

Sometimes it’s the little things. Reverse engineered Gidel PSDB_HDMI AD9889B TX output pattern generated by fully reverse engineered Gidel ProcSpark II ep2c35 FPGA PCI board. I wrote a new controller IP for the ep1c4 FPGA that sits in between the PCI bus and the main FPGA.

I am on too many social networks

Wrote some i2c initialization for the ad9889 HDMI tx on a development board, was certain that I got it wrong because it looked like this, spent 2 hours tweaking it. Then I checked the schematic vs the default pin mappings provided with the kit in the golden top file - spot the bug.