Jörg Mische
@bobbl.bsky.social
📤 10
📥 34
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FPGA, RISC-V, NoC, hard real-time, lightweight cryptography
QEMU has no user-mode emulation for TriCore, but Infineon's TSIM offers some virtual I/O that can be used instead.
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User-mode emulation for TriCore with TSIM and the GNU toolchain
QEMU User-mode Emulation is a practical solution for testing algorithms directly without having to set up a microcontroller system and boot it every time you test. Unfortunately, QEMU only supports fu...
https://bobbl.github.io/tricore/2025/11/12/tricore-user-mode-emulation.html
6 months ago
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PunyCC finally supports OpenRISC. The branch delay slots were really challenging. But now you can build cross compilers to and from any of the other supported ISAs: x86, ARM Thumb, RISC-V and WASM.
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GitHub - bobbl/punycc: Very small self-compiling cross compiler for a subset of C
Very small self-compiling cross compiler for a subset of C - bobbl/punycc
https://github.com/bobbl/punycc
6 months ago
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Puny C Compiler, one of the smallest cross compilers in the world, now supports WebAssembly in addition to ARMv6-M, RISC-V RV32IM and Intel x86-32.
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GitHub - bobbl/punycc: Very small self-compiling cross compiler for a subset of C
Very small self-compiling cross compiler for a subset of C - bobbl/punycc
https://github.com/bobbl/punycc
about 2 years ago
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reposted by
Jörg Mische
Steve Klabnik
over 2 years ago
damn, RIP.
twitter.com/Bertrand_Mey...
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Here I am!
over 2 years ago
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you reached the end!!
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