#Intel #NovaLakeL PCIDIDs appeared in the coreboot source code: review.coreboot.org/c/coreboot/+...

#AMD released the "AMD64 Architecture Programmer’s Manual Volume 4: 128-Bit, 256-Bit, and 512-Bit Media Instructions" 26568 pdf v3.26 docs.amd.com/v/u/en-US/26... This describes instructions up to #Zen5 #AVX512_BMM #AVX512_FP16 #AVX_NE_CONVERT #AVX_IFMA #AVX_VNNI_INT8 from #Zen6 are missing

Thanks to @TDevilfish insightful comments, now is clear that classic #AMD #Zen6 CCD will come with SP8 socket only in the server space. This lead to the revelation is that B50F00 CPUID is means the #Venice with dense CCD.

#Intel #NovaLakeL CPUID 300F30 appeared in coreboot source: review.coreboot.org/c/coreboot/+... Nothing new, just good to see

#Intel 2026+ projects 001 GitHub: github.com/InstLatx64/I...

#AMD #Ryzen #9950X3D2 seems to be an interesting fix for the CPUID.80000006h.EDX[L3size] glitch: this 6 asymmetric SKUs reports 192MB L3 in this field. CPUID.8000001Dh is OK.

#Intel refreshed the "Intel Resource Director Technology (Intel RDT) Architecture Specification" to 1.3 356688-004 cdrdv2-public.intel.com/851356/35668... #DiamondRapids

#AMD #GlacierPeak #PineRidge Embedded Ryzen codenames docs.amd.com/v/u/en-US/ug...

#Intel #PantherLake CPUID C06C2, C06C3 SpecUpdate 869992-001 www.intel.com/content/www/...

Intel laptop SKU chart, #Haswell -> #PantherLake Launch year, core count, freq, GPU data, etc. cdrdv2-public.intel.com/843334/Intel...

14 #Intel #PantherLake SKUs on ark: www.intel.com/content/www/...

Great documentation archive, despite the name it's not just x86: kib.kiev.ua/x86docs/

#Intel #XeonE CPUIDs: #Greenlow 506E3 ( #Skylake ) #Mehlow 906ED ( #CoffeeLake ) #Tatlow A0671 ( #RocketLake ) #Catlow B0671 ( #RaptorLake ) #Dunlow 300F10? ( #NovaLake ) Source: x.com/x86deadandba...

Another interesting #Intel #DiamondRapids info from Linux kernel list: It seems DMR has multiple L3 cache, one per #CBB (Core Building Block = CPU die) lore.kernel.org/all/20251227...

#AMD released the "Introducing AMD #CDNA4 Architecture" white paper pdf: www.amd.com/content/dam/...

New #AMD #Zen6 CPUIDs: - BB0F00 [1] - BD0F80 [1] - BE0F00 [1] Source: [1]: github.com/gcc-mirror/g... GitHub: github.com/gcc-mirror/g...

#AVX_VNNI_INT16 & #AVX10_VNNI_INT enable full 10-digit ASCII->int conversion (0000000000–9999999999) using only two multiplication stages, since 10^n=2^n·5^n and 2^n is just shifts. Non-AI human code #ArrowLake #LionCove #Skymont #PantherLake #CougarCove #Darkmont #NovaLake #PantherCove #ArcticWolf

#Intel Data Streaming Accelerator User Guide 4.0: cdrdv2-public.intel.com/759709/35321...

According to #AMD #Venice PMC, #Zen6 will have 6 integer schedulers. Likely 6 AGU-ALU pairs, similar to Zen4’s 4 and will catch up with #Intel #LionCove. Since Zen6 seems focused on bandwidth, hopefully the 2 loads/clk limit for VEC registers will finally be gone.

According to this GCC patch, the entire B80Fxx-BE0F7x CPUID range is mapped to #AMD #Zen6 cores, except for the BD0F0x-BD0F7x range. I think this exception might be some #Zen5, maybe the unreleased #SonomaValley? github.com/gcc-mirror/g...

First official #AMD #Zen6 docs: "Performance Monitor Counters for AMD Family 1Ah Model 50h-57h Processors" 69163 v1.00 docs.amd.com/v/u/en-US/69... Confirmed features: PMCx003: #FP16 PMCx2C0: #MemoryProfiler PMCx0AF: 6 Integer Scheduler (vs 1 central of #Zen5)

New #Intel #TDX docs: Intel® TDX Module ABI Specification cdrdv2-public.intel.com/871617/intel... Intel® TDX Module Base Architecture Specification cdrdv2-public.intel.com/871616/intel... Intel® TDX Migration Architecture Specification cdrdv2-public.intel.com/858623/intel...

Actually, this die configuration is not new information, it was already mentioned on this removed slide: (Although the CPU die's CBB name is seems still new.)

#Intel #18A Resource Guide: www.intel.com/content/www/...

Insightful Linux kernel patch: #Intel #DiamondRapids CPU chip = Core Building Block (CBB) and unlike #GraniteRapids they do not have an IMC. #DMR can have a chip with two "Integrated I/O and one memory hub (IMH)". DMR goes even further than #ClearwaterForest where the IMC is on the Base Tile. 1/2

#Intel released the " #Xeon6 Tuning and Optimization Guide for HPC Applications" 858491 pdf v1.1 cdrdv2-public.intel.com/858491/85849...

#Intel #XED commit, sync with 60th ISA Ext guide: #NovaLake (#CoyoteCove + #ArcticWolf) supports #AVX10_1 #AVX10_2 #APX #MOVRS #SM4 github.com/intelxed/xed...

#Intel XeSS2 page: www.intel.com/content/www/...

#Intel released the "Priority Core Turbo Technology (PCT Technology)" Technical Article 846906 v1.5.1 pdf cdrdv2-public.intel.com/846906/84690...

#AMD #EPYC2005 page: www.amd.com/en/products/... Product brief: www.amd.com/content/dam/...

#Intel refreshed the "Intel XMP 3.0 Memory for Intel Core™ Processors Datasheet" xlsx: www.intel.com/content/www/...

#Intel released the "Intel #Xeon6 vs #AMD #EPYC Competitive Infographic" pdf: cdrdv2-public.intel.com/859022/intel...

New CPUID dumps: #AMD -- #EPYC 4124P ( #Raphael, #Zen4) A60F12 -- 2C+4c #Ryzen 5 Pro 215 ( #HawkPoint2, Zen4) #Hygon -- C86-4G (OPN:3450G) 910F00 GitHub: github.com/InstLatx64/I...

InstLatX64 refresh: -- #AMD #Ryzen 9 9950X ( #GraniteRidge, #Zen5) B40F40 256b+512b FPU x64 InstLat dump refresh -- #Qualcomm Orion X1 F4A and 600F01 CPUID dumps -- InstLat capabilities: 5396 entries, up to #AVX512BMM GitHub: github.com/InstLatx64/I...

#Intel released the "Trust Domain Extensions (Intel TDX) Module Extension for Pre-Migration" 869278 001US pdf: cdrdv2-public.intel.com/869278/TDX%2...

#AMD released the "PQOS White Paper for AMD #EPYC 9004 and 9005 Series Processors" 69127 1.00 pdf docs.amd.com/v/u/en-US/69...

#Intel released the "Intel Architecture Memory Protections for Confidential Computing" Technical Paper 869103 pdf www.intel.com/content/www/...

#AMD "Beyond Cloud First: The Rise of Hybrid Consistency" pdf: www.amd.com/content/dam/...

It seems, #AMD utilizes their #Zen5 #FireRange CPUs in the embedded server space too: #EPYC9005 - #SP5 #EPYC8005 - #SP6 #EPYC4005 - #AM5 #EPYC2005 - #FL1 docs.amd.com/v/u/en-US/ug...

If the CCD of #Zen6 #Threadripper is - classic, like in #Zen4 and #Zen5, then the maximum number of cores is only 4x12=48; - dense, then the number of cores can be 128, but with a frequency limit, like in #Zen4c (~3.1 GHz) and #Zen5c (~3.7 GHz);

The problem with #AMD #Zen6 #Threadripper is that the components revealed so far (12-core classic, 32-core dense, 4 CCD/IO chips) cannot be used to build a 96-core, frequency-optimized version in the size of #SP8 socket, which could replace the current top-SKU 9995WX.

The #Zen6-based #AMD #Threadripper is missing from this chart. I don't recall seeing its codename, does it even exist?

#AMD refreshed the "Revision Guide for AMD Family 19h Models 10h-1Fh Processors" 57095 to v1.05 pdf ( #Genova #Zen4 B0 CPUID A10F11 #EPYC ) docs.amd.com/v/u/en-US/57...

#AMD refreshed the "Revision Guide for AMD Family 19h Models A0h-AFh Processors" 57926 to v1.05 pdf ( #Bergamo #Zen4c A0 CPUID AA0F02 #EPYC ) docs.amd.com/v/u/en-US/57...

#Intel released the 60th edition of the ISA Extensions Reference with official announcement of #AVX10 and #APX support on #NovaLake, and FP8 type clarifications. Download: cdrdv2-public.intel.com/869288/31943... #DiamondRapids #NovaLake #WildcatLake #PantherCove #CoyoteCove #ArcticWolf

Today I learned: At least 3 #AVX512 levels were planned, but they never released: #AVX512QVNNI - byte form of 4VNNIW, it would extinct with KNM/MIC; #AVX512DFMA - VDF[,n]MADD[P,S][S,D] - I have no idea what the difference between FMA & DFMA; #AVX512BITALG2 - this is the most interesting for me; 1/3

The current VNNI landscape #AMD #Intel #Zen6 #AVX10_2 #AVX_VNNI #AVX_VNNI_INT8 #AVX_VNNI_INT16 #DiamondRapids #NovaLake

#AMD #Zen6 znver6 ISA: - #AVX512_BMM (CPUID.80000021.EAX[23], VBMACOR16x16x16, VBMACXOR16x16x16, VBITREV) - #AVX512_FP16 - #AVX_NE_CONVERT - #AVX_IFMA - #AVX_VNNI_INT8 Source: sourceware.org/pipermail/bi...

Visualised AMD-SB-7055 issue on a #Zen5 #AMD #Ryzen 9 9950X. The zeroed #RDSEED rate can exceed the 3% under concurrent execution... www.amd.com/en/resources...

#Intel refreshed the "Intel Virtualization Technology for Directed I/O Architecture Specification" pdf to 5.1 cdrdv2-public.intel.com/868911/D5139...