#Intel released the 59th edition of the ISA Extensions Reference with some #PantherCove, #CoyoteCove and #ArcticWolf microarchitecture details: #DiamondRapids #NovaLake #WildcatLake Download: cdrdv2-public.intel.com/865891/31943... #AMX_TRANSPOSE removed

The redesigned #AMD Technical Information Portal: docs.amd.com

An example of how virtualization distorts CPUID. For this reason, they should not be included in my collection, similar to Engineering Samples. #AMD #Zen5 #Threadripper

Collection of charts for earlier #AMD #Zen5 and #Zen6 versions: github.com/InstLatx64/I... github.com/InstLatx64/I... Latest versions are v1.20 and v1.24: github.com/InstLatx64/I... github.com/InstLatx64/I...

#AMD E-SMI (EPYC System Management Interface) and HSMP (Host System Management Port) kernel module got #Zen6 #Venice #SP7 CPUID B50F00 support: github.com/amd/esmi_ib_... github.com/amd/amd_hsmp...

#Intel refreshed the xAPIC depreciation plan with #NovaLake and #DiamondRapids:

New #Intel #PantherLake steppings in coreboot: PTL_B0_3 C06C3 review.coreboot.org/c/coreboot/+...

#Intel defeatured Scalable IO Virtualization in the latest #SapphireRapids and #EmeraldRapids Specification Update: www.intel.com/content/www/... #SPR SpecUpdate 016: edc.intel.com/output/Downl... #EMR SpecUpdate 016: edc.intel.com/output/Downl...

#Intel xAPIC depreciation plan 1.0: www.intel.com/content/www/...

This #AMD mitigation paper reveals the meaning of 3 new CPUID bits: Fn8000_0021 ECX[2]: TSA_L1_NO Fn8000_0021 ECX[1]: TSA_SQ_NO Fn8000_0021 EAX[5]: VERW_CLEAR www.amd.com/content/dam/...

It's too bad that this AVX3.1 nomenclature disappeared. I think it is much more seamless, like SSE4.2, SSE5 (original name of AMD XOP) or Armv8.2. AMX2 and AMX3.1 would be also better.

I've summarized the #Zen6 info into a #Zen5 analog chart. It seems that the homogeneous era is over at #AMD as well, there will be SKUs that will have 256b and 512b FPUs same time. I think the ISA homogeneity will remain.

These are my expectations for #AMD #Zen6. #Zen5 is a very strong architecture, but it has some weak point that Zen6 will hopefully fix. (The Zen5 512/256b FPU size is not segmented along the Classic/Dense axis, but along the MCM=Multi-Chip Module/SCM=Single-Chip Module axis)

Here is an early mention of 512b vectors in a 2009 #Intel #Nehalem optimization slide:

#Intel #Skymont vs. #Darkmont, spot the difference:

#Intel #PantherLake got perfmon support: github.com/intel/perfmo... According to this #CougarCove and #Darkmont is similar to #LionCove and #Skymont, just the front-end/branch prediction is different.

#Intel #Xeon #GraniteRapidsD (CPUID A06E1, Intel 3 lithography, #RedwoodCove, FCBGA4368) microcode: winraid.level1techs.com/t/intel-amd-...

I think #AMD #Sorano is TSMC 3nm #Zen5c #EPYC 8005 #TurinD in #SP6 socket

#Intel #PantherLake in CoreBoot source: review.coreboot.org/c/coreboot/+... review.coreboot.org/c/coreboot/+... review.coreboot.org/c/coreboot/+...

#Intel #Xeon #ClearwaterForest (CPUID D06D0, Intel 18A process, #Darkmont based #SierraForest descendant) microcode in a #LGA7529 #Supermicro motherboard: [1]: winraid.level1techs.com/t/intel-amd-... [2]: www.supermicro.com/en/products/...

#AMD #Instinct family chart: www.amd.com/content/dam/... page 7.

Collection of earlier versions of #Intel 2025+ projects: github.com/InstLatx64/I... Latest one is the v059: github.com/InstLatx64/I...

On the #AMD site, this page mentions a 96-core maximum (8 CCDs) for the classic (embedded) #Zen6 based #Venice #EPYC, which is a drop from the 128-core #Zen5 #Turin. I don't know what causes this: CCD size? CCD consumption? Chiplet IO size? docs.amd.com/v/u/en-US/ug... #MRDIMM

#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 1" 24592 pdf to v3.23 with #AVX512 docs.amd.com/v/u/en-US/24...

#Intel microcode refresh 20250812: github.com/intel/Intel-... Release Notes: github.com/intel/Intel-...

According to this CPU-cooler site, AMD #SP7 doesn't look much bigger than #SP5: SP5: 118 * 92.4 * 25 mm [1] SP7: 118 * 101.5 * 25 mm [2] [1]: www.loricooler.com/amd-sp5-lga-... [2]: www.loricooler.com/amd-sp7-sock...

#GMI vs #SSBDCI difference at the physical layer (if I understand correctly): 16 vs 2x32 wires. Has anyone measured the #StrixHalo Core2Core bandwidth? Sources: [1]: www.amd.com/content/dam/... [2]: chipsandcheese.com/p/amds-strix...

There are a few working #PantherLake B0_2 among #Intel test machines: (CPUID C06C2, 12c/12t (4P+4E+4LPE probably), 3000 MHz, no HTT, no AVX512, Intel 18A) intel-gfx-ci.01.org/tree/intel-x... #CougarCove #Darkmont For comparison, #LunarLake was 3100MHz (8c/8t 4P+4LPE) at similar stage

AMD #Zen5 / #Turin / #SP5 vs #Zen6 / #Venice #SP7 max memory bandwidth: 1600/614 > 2.5, this worth a socket change

What does this abbreviation #SSBDCI mean? Will the #AMD #Zen6 also use this?

New #Intel CPUIDs [1]: - #NovaLake 300F10 (Family 18 model 1) - #NovaLakeL 300F30 (Family 18 model 3) New dump: -Core Ultra 9 275HX C0662 #ArrowLakeHX New #AMD #Zen6 Venice #EPYC socket assignments [2]: -B50F00, BC0F00 #SP7 16 m. c. -B90F00, BA0F00 #SP8 8 m. c. GitHub: github.com/InstLatx64/I... 1/2

This Linux kernel patch reveals the #AMD #Zen6 CPUID socket assignments and the maximum supported memory channels per future SP7/8 socket: lore.kernel.org/lkml/2025072... -B50F00, BC0F00 is #SP7, 16 mem channels -B90F00, BA0F00 is #SP8, 8 mem channels

This Linux kernel patch reveals #Intel #NovaLake CPUID 300F10 (Fam 18 Model 1) and #NovaLakeL CPUID 300F30 (Fam 18 Model 3): lore.kernel.org/lkml/2025080... GitHub: github.com/InstLatx64/I...

I just finished my first meaningful #APX code path: #SHA3 / #Keccak1600 on 32 GPR registers: Only 130 uops + a few MOVs. I wonder if it can beat the latency of 35+ uop #AVX512 version on #Intel #DiamondRapids. #Novalake , #PantherCove , #CoyoteCove

#Intel refreshed the Advanced Performance Extensions (#Intel #APX) Architecture Specification to 7.0: cdrdv2-public.intel.com/861610/35582... APX_NCI_NDD_NF = CPUID.(EAX=0x29,ECX=0x00):EBX[0]

#Intel projects 2025+ v53 #PantherLake #NovaLakeU #NovaLakeS #RazerLake #TitanLake #BartlettLake #WildcatLake #GraniteRapids #GraniteRapidsD #DiamondRapids #DiamondRapidsD #CoralRapids #ClearwaterForest #RogueRiverForest #APX #AVX10_1 #AVX10_2 #AVX512 Thx for the feedback @mintsuki.com, G_melo_ding!

AFAIK the only measurable architectural difference between the #AMD #Zen5 versions is the 2/3 clks FADD latency, but not between the Classic/Dense versions, but along the native FPU 512/256b size.

An explicit mention of 512b #AVX10_2 for future #Intel desktop CPUs ( #NovaLake, what else?): github.com/uxlfoundatio...

Agner Fog updated his manuals with the #AMD #Zen5 agner.org/optimize/

A cool list of #Intel projects with CPUIDs and SKUs: www.intel.com/content/www/...

First(?) official mention of #AMD #Sorano (the expected #EPYC 8005 #SP6 socket #Zen5-based #Siena follower): deic.dk/sites/defaul... page 25

#Intel projects 2025+ v50 #PantherLake #NovaLakeU #NovaLakeS #RazerLake #TitanLake #BartlettLake #WildcatLake #GraniteRapids #GraniteRapidsD #DiamondRapids #DiamondRapidsD #CoralRapids #ClearwaterForest #RogueRiverForest #APX #AVX10_1 #AVX10_2 #AVX512

#Intel #GraniteRapids SKU stack: cdrdv2-public.intel.com/860027/Intel...

New CPUIDs: - #AMD #KrackanPoint2 CPUID B60F80 [1] - #Intel #BartlettLake CPUID B06F6 [2] [1]: browser.geekbench.com/v6/cpu/12687... [2]: browser.geekbench.com/v6/cpu/12794... GitHub: github.com/InstLatx64/I...

#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 3 General-Purpose and System Instructions" 24594 to v3.37 #AVX512 #PREFETCHI docs.amd.com/v/u/en-US/24...

#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 2" 24593 pdf to v3.43 with #AVX512 docs.amd.com/v/u/en-US/24...

#AMD released the "Processor Programming Reference (PPR) for AMD Family 1Ah Model 70h, Revision A0 Processors" v3.00 57930 pdf #Zen5 #StrixHalo CPUID B70F00 docs.amd.com/api/khub/doc... "High Bandwidth Chiplet IO: SSBDCI"

#Intel released the SDE 9.58.0 (Software Development Emulator), sync with 57th ISA Ext Guide Download: downloadmirror.intel.com/859732/sde-e... - #DiamondRapids CPUID is 400F10 instead of D0660 (in-line with ISA Ext Guide) - #GraniteRapids256 removed

#Intel refreshed the "Flexible Return and Event Delivery" ( #FRED) 346446 pdf to 9.0: cdrdv2-public.intel.com/819481/34644...

#Intel released the 88th edition of the Software Developer’s Manuals with #SLSM (Static LockStep Mode) integrity feature: CPUID.(EAX=07H,ECX=01H):EDX[24]=SLSM All-in-One: cdrdv2-public.intel.com/858440/32546... Changes: cdrdv2-public.intel.com/858441/25204...