My quick note about #Intel #ArrowLake CPUID C0662 #Skymont and #PantherLake CPUID C06C3 #Darkmont instruction level differences

#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 2" 24593 pdf to v3.44 docs.amd.com/v/u/en-US/24...

#AMD has updated the "Seamless Firmware Maintenance (SFS) Specification" pdf 58604 to v0.76: docs.amd.com/v/u/en-US/58...

New #Intel #TDX docs: Intel TDX Module Extension for Quoting cdrdv2.intel.com/v1/dl/getCon...

What CCD is used in #AMD #Sorano #EPYC8005? 84 cores is quite a strange number, 12*7? www.amd.com/en/blogs/202...

#AMD released the "CPU Timing and Power Side Channel Guidance" pdf 71030 v1.1: docs.amd.com/v/u/en-US/71...

#AMD released the 7th #Zen6 pdf "Guest PMC Event Filtering" 69202 v1.00: docs.amd.com/v/u/en-US/69... CPUID Fn8000_000A_ECX[GuestPmcFiltering], bit 3 #Virtualization

#Intel refreshed the #AVX10_2 specification to 6.0: cdrdv2-public.intel.com/913918/36105... #AVX10_VNNI_INT renamed to #AVX10_V1_AUX

#Intel refreshed the Advanced Performance Extensions (#Intel #APX) Architecture Specification to 8.0: cdrdv2-public.intel.com/913917/35582...

#AMD released the 6th #Zen6 pdf "CPPC Performance Priority" 69206 v1.00: docs.amd.com/v/u/en-US/69... #CPPC

#Intel released the SDE 10.7 (Software Development Emulator) with Indirect Branch History Fence ( #IBHF) instruction support and refreshed CPUID dumps: www.intel.com/content/www/... #NovaLake #DiamondRapids #APX #AVX10_2

#AMD released the 5th #Zen6 pdf "RMPOPT" 69203 v1.00: docs.amd.com/v/u/en-US/69... #RMPOPT #Virtualization

#AMD released the 4th #Zen6 pdf "RMP Dirty" 69203 v1.00: docs.amd.com/v/u/en-US/69... #RMPCHKD #Virtualization

#AMD has removed the public access to the #Zen6 "Performance Monitoring Counters for AMD Family 1Ah Model 50h-57h Processors" pdf. Perhaps a new version reveals too much detail. Bugzilla has archived v1.00: bugzilla.kernel.org/attachment.c...

#AMD has re-released PDFs 69191 and 69192, removing the "AMD Confidential" headers. #AVX512_BMM specification: docs.amd.com/v/u/en-US/69... #FRED specification: docs.amd.com/v/u/en-US/69...

This snow report was the inspiration for this #AMD #Zen codename table. Sources included. #Zen2 #Zen3 #Zen4 #Zen5 #Zen6 #Zen7

There are a few working #WildCatLake among #Intel test machines: (CPUID D06D1, 6c/6t (2P+4LPE probably), 2500 MHz base freq, no HTT, no AVX512, I think Intel 18A) intel-gfx-ci.01.org/tree/intel-x... #CougarCove #Darkmont

According to this LLVM patch, #AMD CPUID BD0F00 is #Annapurna, a #Zen5 based #EPYC Embedded for Network Control Planes: github.com/llvm/llvm-pr...

#Intel #Xeon600 Processors for Workstation (GNR-W) - Turbo Tables: www.intel.com/content/www/... #GraniteRapidsW #GNRW

#Intel microcode refresh 20260211: github.com/intel/Intel-... CSV: github.com/intel/Intel-...

#Intel released the 90th edition of the Software Developer’s Manuals with canonized #FRED, #ArchitecturalPEBS, Asymmetric RDT-M & RDT-A All-in-One: cdrdv2-public.intel.com/874240/32546... Changes v82: cdrdv2-public.intel.com/874239/25204... #LKGS, #PBNDKB

New CPUID dump: -- 128-Core #AMD #EPYC 9754 ( #Bergamo top-SKU, #Zen4c) AA0F02 New Intel codenames: - #Dunlow (LGA1954 entry server [1]) - #TitanLake, #HammerLake [2] - LGA1954 socket info #NovaLake, #RazorLake [2] #AMD #Venice info: - B50F00, B90F00 = Dense - BA0F00, BC0F00 = Classic 1/2

Has anyone come across the pin number of the #AMD #SP8 socket? Maybe e.g. a cooler or motherboard manufacturer has already posted it somewhere...

SDE 10.5.0 (Software Development Emulator) Release Notes:

Fortunately, all 11 #Intel #GraniteRapidsW SKUs use dual FMA: www.intel.com/content/www/...

Official #Intel #GraniteRapidsW SKU list: www.intel.com/content/www/... #GNR_W #AVX512 #AVX10_1 #AMX_FP16

#Intel released the SDE 10.5.0 (Software Development Emulator), sync with 60th ISA Ext Guide: www.intel.com/content/www/... #NovaLake #DiamondRapids #APX #AVX10_2

One possible application of the #AVX512_BMM VPMACOR16x16x16 instruction is the compact index2msk function: if src2 is a full mask and src3 contains variably shifted masks, then VPMACOR16x16x16 will collect them into a single word. The order and repetitions are arbitrary.

Third official #AMD #Zen6 docs: "AMD64 Bit Matrix Multiply and Bit Reversal Instructions" specification #AVX512_BMM 69192 v1.00 pdf: docs.amd.com/v/u/en-US/69...

#Intel refreshed the "In-Memory Analytics Accelerator Architecture Specification" 350295-007 pdf to 3.0: www.intel.com/content/www/...

#AMD released the "AMD64 Flexible Return and Event Delivery (FRED) Virtualization" 69191 v1.00 pdf for #Zen6: docs.amd.com/v/u/en-US/69...

#Intel Software Guard Extensions #SGX Page: www.intel.com/content/www/...

#AMD refreshed the "Using #SEV with AMD #EPYC Processors" Guide 58207 v2.0 docs.amd.com/v/u/en-US/58...

#Intel refreshed the "Hardware Features and Behavior Related to Speculative Execution" page and pdf: www.intel.com/content/www/... Pdf: cdrdv2-public.intel.com/758913/Hardw...

My current knowledge of #AMD #Zen topology:

Agner Fog has new version of the Nan propagation paper: www.agner.org/optimize/nan...

#Intel #NovaLakeL PCIDIDs appeared in the coreboot source code: review.coreboot.org/c/coreboot/+...

#AMD released the "AMD64 Architecture Programmer’s Manual Volume 4: 128-Bit, 256-Bit, and 512-Bit Media Instructions" 26568 pdf v3.26 docs.amd.com/v/u/en-US/26... This describes instructions up to #Zen5 #AVX512_BMM #AVX512_FP16 #AVX_NE_CONVERT #AVX_IFMA #AVX_VNNI_INT8 from #Zen6 are missing

Thanks to @TDevilfish insightful comments, now is clear that classic #AMD #Zen6 CCD will come with SP8 socket only in the server space. This lead to the revelation is that B50F00 CPUID is means the #Venice with dense CCD.

#Intel #NovaLakeL CPUID 300F30 appeared in coreboot source: review.coreboot.org/c/coreboot/+... Nothing new, just good to see

#Intel 2026+ projects 001 GitHub: github.com/InstLatx64/I...

#AMD #Ryzen #9950X3D2 seems to be an interesting fix for the CPUID.80000006h.EDX[L3size] glitch: this 6 asymmetric SKUs reports 192MB L3 in this field. CPUID.8000001Dh is OK.

#Intel refreshed the "Intel Resource Director Technology (Intel RDT) Architecture Specification" to 1.3 356688-004 cdrdv2-public.intel.com/851356/35668... #DiamondRapids

#AMD #GlacierPeak #PineRidge Embedded Ryzen codenames docs.amd.com/v/u/en-US/ug...

#Intel #PantherLake CPUID C06C2, C06C3 SpecUpdate 869992-001 www.intel.com/content/www/...

Intel laptop SKU chart, #Haswell -> #PantherLake Launch year, core count, freq, GPU data, etc. cdrdv2-public.intel.com/843334/Intel...

14 #Intel #PantherLake SKUs on ark: www.intel.com/content/www/...

Great documentation archive, despite the name it's not just x86: kib.kiev.ua/x86docs/

#Intel #XeonE CPUIDs: #Greenlow 506E3 ( #Skylake ) #Mehlow 906ED ( #CoffeeLake ) #Tatlow A0671 ( #RocketLake ) #Catlow B0671 ( #RaptorLake ) #Dunlow 300F10? ( #NovaLake ) Source: x.com/x86deadandba...

Another interesting #Intel #DiamondRapids info from Linux kernel list: It seems DMR has multiple L3 cache, one per #CBB (Core Building Block = CPU die) lore.kernel.org/all/20251227...